CoWoS

TSMC Digs Trenches In Search Of Higher Performance

IEDM 2019 Interconnects Packaging Process Technologies December 14, 2019 0

TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.

TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging

Packaging Process Technologies SEMICON West 2019 VLSI 2019 July 28, 2019 3

An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.

TSMC Demonstrates A 7nm Arm-Based Chiplet Design for HPC

Interconnects Packaging Server Processors VLSI 2019 June 22, 2019 0

A look at a high-performance 7nm Arm-based chiplet architecture which was recently presented by TSMC at the 2019 VLSI Symposium.