CoWoS – WikiChip Fuse

Interconnects Packaging Process Technologies

TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications

March 3, 2020May 25, 2021 David Schor 2.5D packaging, 5 nm, 7 nm, CoWoS, interposer

TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The new technology is ready for next-generation 5-nanometer HPC applications.

IEDM 2019 Interconnects Packaging Process Technologies

TSMC Digs Trenches In Search Of Higher Performance

December 14, 2019May 25, 2021 David Schor 2.5D packaging, CoWoS, DTC, IEDM, IEDM 2019, MiM, TSMC

TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.

Packaging Process Technologies SEMICON West 2019 VLSI 2019

TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging

July 28, 2019May 25, 2021 David Schor 3D packaging, 3nm, 5nm, 6nm, 7nm, CoWoS, InFO, InFO_AiP, InFO_MS, InFO_oS, N5, N5P, N6, N7, N7P, SemiConWest, SoIC, TSMC, VLSI 2019, VLSI Symposium

An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.

Interconnects Packaging Server Processors VLSI 2019

TSMC Demonstrates A 7nm Arm-Based Chiplet Design for HPC

June 22, 2019May 25, 2021 David Schor 7nm, ARM, ARMv8, chiplet, Cortex-A72, CoWoS, LIPINCON, TSMC, VLSI 2019, VLSI Symposium

A look at a high-performance 7nm Arm-based chiplet architecture which was recently presented by TSMC at the 2019 VLSI Symposium.