WikiChip Fuse
TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications

TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The new technology is ready for next-generation 5-nanometer HPC applications.

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TSMC Digs Trenches In Search Of Higher Performance

TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.

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TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging

An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.

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TSMC Demonstrates A 7nm Arm-Based Chiplet Design for HPC

A look at a high-performance 7nm Arm-based chiplet architecture which was recently presented by TSMC at the 2019 VLSI Symposium.

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