WikiChip Fuse
CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active interposer die.

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A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC

A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered accelerator.

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Arm Launches New Neoverse N1 and E1 Server Cores

Affirming their commitment to infrastructure, Arm is launching two new server-grade platforms – the Neoverse N1 and E1. The new platforms are designed to offer new Arm-based high-performance compute and high-throughput performance IP options.

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Esperanto exits stealth mode, aims at AI with a 4,096-core 7nm RISC-V monster

Exiting stealth mode, Esperanto, a small start-up lead by Dave Ditzel has unveiled their high-performance RISC-V cores they have been working on. Their first product will be a 4,096-core manycore processor designed for accelerating AI workloads.

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Intel silently launches Knights Mill

This morning Intel quietly released three Xeon Phi SKUs up to 72 cores based on Knights Mill, a Deep Learning specific derivative of Knights Landing.

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The 2,048-core PEZY-SC2 sets a Green500 record

PEZY-SC2 is PEZY’s newest 16nm a many-core processor featuring 2,048 cores that is powering the world’s most power-efficient supercomputer. The chip is the first to use a unique 3D packaging interconnect technology known as TCI in order to achieve a memory bandwidth of over 2 TB/s.

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