We have known for a while now that GlobalFoundries was planning an aggressive shrink of their 14nm process. At the 63rd IEEE International Electron Devices Meeting (IEDM), GlobalFoundries presented their “late” paper on their 7nm process – “7nm Leading Performance” or “7LP” for short. The paper was presented by Dr. Premlatha Jagannathan. Jagannathan is responsible for the advanced technology materials engineering at GlobalFoundries.
The focus of the paper was about their 7nm CMOS technology platform for mobile and high-performance computing applications. The paper presented the work that was done by their 7nm development team.
We will start off with the laundry list of features and then dive into the specifics. The general attributes of this process are:
- Targets Mobile, SoC, HPC
- 2.8x routed logic density over their 14nm
- Provides 40% higher performance or 55% lower power over their 14nm
- Immersion lithography and advanced optical patterning (SADP, SAQP)
- Cobalt introduced for liner and the caps at the SAQP-critical layers
- EUV insertion plan in place, undefined timeline (i.e., “when ready”)
- Backbone of their next-generation ASIC services
- Complete set of foundation and complex IP available (e.g., core, peripherals, SerDes, Memories, 2 & 2.5D packaging)
14nm Reference Technology
Throughout the IEDM presentation, they made many comparisons against a 14nm reference node. This 14nm node was initially presented by Samsung at the 2014 IEEE International Solid-State Circuits Conference (ISSCC). Their 14nm node has been in production for over two years and has been used for a very diverse set of applications including high-performance computing, networks, and mobile application processors. A well-known example of such product is AMD’s Zen microarchitecture.
With that respect, their 7nm brings a full node density and performance scaling over the 14nm reference.
The key technology dimensions are shown below.
|GlobalFoundries 7nm Process|