Skip to content
Friday, February 3, 2023
Latest:
  • A Look At AMD’s 3D-Stacked V-Cache
  • IEDM 2022: Did We Just Witness The Death Of SRAM?
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores
  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications
WikiChip Fuse

WikiChip Fuse

Your Chips and Semi News

  • Home
  • Account
  • Main Site
  • Architectures
    • x86
    • ARM
    • RISC-V
    • Power ISA
    • MIPS
  • Supercomputers
  • 14 nm
  • 12nm
  • 10nm
  • 7nm
  • 5nm

Spring Hill

Neural Processors Supercomputing 19 

Intel Starts Shipping Initial Nervana NNP Lineup

December 6, 2019May 25, 2021 David Schor AI, inference, Intel, neural processors, NNP, NNP-T, NPP-L, OCP Accelerator Module (OAM), Spring Crest, Spring Hill, Supermicro, training

Intel starts shipping its initial Nervana NNP lineup for both inference and training acceleration with four initial models in three different form factors.

Read more
Architectures Hot Chips 31 Neural Processors 

Intel Spring Hill: Morphing Ice Lake SoC Into A Power-Efficient Data Center Inference Accelerator

October 20, 2019May 25, 2021 David Schor 10nm, AI, inference, Intel, Nervana, neural processors, Spring Hill, Sunny Cove, Tensilica Vision DSP, Tensilica Vision P6, x86

First detailed at Hot Chips 31, Intel Spring Hill morphs the Ice Lake SoC into a highly power-efficient data center inference accelerator.

Read more
Architectures Neural Processors 

Intel’s Spring Crest NNP-L Initial Details

April 14, 2019May 25, 2021 David Schor 16nm, AI, inference, Intel, Lake Crest, Linley Processor Conference, Nervana, neural processors, NNP, NNP-I, NNP-L, Spring Crest, Spring Hill, training

An initial look into Intel’s upcoming Nervana Neural Network Processor (NNP) accelerators.

Read more

Top Six Articles

  • A Look At Intel 4 Process Technology
  • N3E Replaces N3; Comes In Many Flavors
  • IEDM 2022: Did We Just Witness The Death Of SRAM?
  • A Look At The Ice Lake Thunderbolt 3 Integration
  • Arm’s New Cortex-M55 Breathes Helium
  • The Mesh Network For Next-Generation Neoverse Chips

Recent

  • A Look At AMD’s 3D-Stacked V-Cache

    A Look At AMD’s 3D-Stacked V-Cache

    December 27, 2022December 27, 2022 David Schor
  • IEDM 2022: Did We Just Witness The Death Of SRAM?

    IEDM 2022: Did We Just Witness The Death Of SRAM?

    December 14, 2022December 15, 2022 David Schor
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    November 1, 2022November 2, 2022 David Schor
  • Intel, SiFive Demo High-Performance  RISC-V Horse Creek Dev Platform On Intel 4 Process

    Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process

    October 7, 2022October 7, 2022 David Schor
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    October 4, 2022October 4, 2022 David Schor
  • Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    October 1, 2022October 3, 2022 David Schor

Random Picks

Intel Announces a 5 GHz Core i7-8086K, Launches on the 40th Anniversary of the 8086

Intel Announces a 5 GHz Core i7-8086K, Launches on the 40th Anniversary of the 8086

June 5, 2018May 25, 2021 David Schor
Intel Launches Desktop Xeon E, Their Fastest Entry-Level Workstation Processors

Intel Launches Desktop Xeon E, Their Fastest Entry-Level Workstation Processors

July 13, 2018May 25, 2021 David Schor
VLSI 2018: Samsung’s 2nd Gen 7nm, EUV Goes HVM

VLSI 2018: Samsung’s 2nd Gen 7nm, EUV Goes HVM

August 4, 2018May 25, 2021 David Schor
Intel Reveals 10nm Sunny Cove Core, a New Core Roadmap, and Teases Ice Lake Chips

Intel Reveals 10nm Sunny Cove Core, a New Core Roadmap, and Teases Ice Lake Chips

December 23, 2018May 25, 2021 David Schor
Arm Launches New Neoverse N2 and V1 Server CPUs: 1.4x-1.5x IPC, SVE, and ARMv9

Arm Launches New Neoverse N2 and V1 Server CPUs: 1.4x-1.5x IPC, SVE, and ARMv9

April 27, 2021May 23, 2021 David Schor

Random Tags

2.5D packaging 3 nm 3D packaging 5 nm 7 nm 7nm 10 nm 10nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 Cortex edge computing EMIB EUV FinFET GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel Intel 7 ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

Reincarnating The 6502 Using Flexible TFT Tech For IoT

Reincarnating The 6502 Using Flexible TFT Tech For IoT

May 8, 2022May 8, 2022 David Schor
Intel Unveils Foveros Omni And Foveros Direct; Leveraging Hybrid Bonding

Intel Unveils Foveros Omni And Foveros Direct; Leveraging Hybrid Bonding

July 26, 2021July 26, 2021 David Schor
TSMC 2021 Foundry Update: Automotive, Networking, and HPC Roadmap

TSMC 2021 Foundry Update: Automotive, Networking, and HPC Roadmap

July 6, 2021July 6, 2021 David Schor
SEMICON West 2019: ASML EUV Update

SEMICON West 2019: ASML EUV Update

July 21, 2019May 25, 2021 David Schor
A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

June 11, 2021June 11, 2021 David Schor
A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip

A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip

November 16, 2019May 25, 2021 David Schor
AMD 3D Stacks SRAM Bumplessly

AMD 3D Stacks SRAM Bumplessly

June 7, 2021June 7, 2021 David Schor

ARM WorldView All

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
Architectures Mobile Processors 

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

June 28, 2022June 28, 2022 David Schor
Arm Unveils Next-Gen Flagship Core: Cortex-X3
Mobile Processors 

Arm Unveils Next-Gen Flagship Core: Cortex-X3

June 28, 2022June 28, 2022 David Schor
Arm Introduces The Cortex-A715
Architectures Mobile Processors 

Arm Introduces The Cortex-A715

June 28, 2022June 29, 2022 David Schor
Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor

About

WikiChip
WikiChip is an independent publisher based in New York. The WikiChip Fuse section publishes chips and semiconductor related news with our main site offering in-depth semiconductor resources and analysis.

WikiChip Links

  • Main Site
  • WikiChip Fuse
  • Newsletter
  • Main Site
  • WikiChip Fuse

Copyright © 2023 WikiChip LLC. All rights reserved.