Skip to content
Monday, January 30, 2023
Latest:
  • A Look At AMD’s 3D-Stacked V-Cache
  • IEDM 2022: Did We Just Witness The Death Of SRAM?
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores
  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications
WikiChip Fuse

WikiChip Fuse

Your Chips and Semi News

  • Home
  • Account
  • Main Site
  • Architectures
    • x86
    • ARM
    • RISC-V
    • Power ISA
    • MIPS
  • Supercomputers
  • 14 nm
  • 12nm
  • 10nm
  • 7nm
  • 5nm

OCP Accelerator Module (OAM)

Interconnects Packaging 

OCP Makes a Push for an Open Chiplet Marketplace

January 4, 2020May 25, 2021 David Schor 2.5D packaging, Advanced Interface Bus (AIB), chiplet, EMIB, interposer, OCP Accelerator Module (OAM), OCP Open Domain-Specific Architecture (ODSA), Open Compute Project (OCP)

Jumping ahead of emerging semiconductor trends, the OCP new Open Domain-Specific Architecture subgroup makes a push for an open and standardized chiplet interface and marketplace.

Read more
Architectures Hot Chips 31 Neural Processors 

A Look At The Habana Inference And Training Neural Processors

December 15, 2019May 25, 2021 David Schor 16nm, AI, Gaudi, Goya, Habana Labs, Hot Chips, Hot Chips 31, inference, neural processors, OCP Accelerator Module (OAM), training

A look at the Habana inference and training neural processors designed for the acceleration of data center workloads.

Read more
Neural Processors Supercomputing 19 

Intel Starts Shipping Initial Nervana NNP Lineup

December 6, 2019May 25, 2021 David Schor AI, inference, Intel, neural processors, NNP, NNP-T, NPP-L, OCP Accelerator Module (OAM), Spring Crest, Spring Hill, Supermicro, training

Intel starts shipping its initial Nervana NNP lineup for both inference and training acceleration with four initial models in three different form factors.

Read more
Architectures Hot Chips 31 Linley Processor Conference Neural Processors 

A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor

November 10, 2019May 25, 2021 David Schor 16FF+, 16nm, AI, bfloat16, Hot Chips, Hot Chips 31, Intel, Linley Processor Conference, Nervana, neural processors, NNP, NNP-T, OCP Accelerator Module (OAM), training

A look at the microarchitecture of Intel Nervana next-generation data center training neural processor, codename Spring Crest.

Read more

Top Six Articles

  • A Look At Intel 4 Process Technology
  • A Look At AMD’s 3D-Stacked V-Cache
  • TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO
  • IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery
  • Intel 2021 Process Technology Update: Intel 7, Intel 4, Intel 3, and Intel 20A
  • Intel Unveils Foveros Omni And Foveros Direct; Leveraging Hybrid Bonding

Recent

  • A Look At AMD’s 3D-Stacked V-Cache

    A Look At AMD’s 3D-Stacked V-Cache

    December 27, 2022December 27, 2022 David Schor
  • IEDM 2022: Did We Just Witness The Death Of SRAM?

    IEDM 2022: Did We Just Witness The Death Of SRAM?

    December 14, 2022December 15, 2022 David Schor
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    November 1, 2022November 2, 2022 David Schor
  • Intel, SiFive Demo High-Performance  RISC-V Horse Creek Dev Platform On Intel 4 Process

    Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process

    October 7, 2022October 7, 2022 David Schor
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    October 4, 2022October 4, 2022 David Schor
  • Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    October 1, 2022October 3, 2022 David Schor

Random Picks

Apple’s iMac Pro Xeon W are ready

Apple’s iMac Pro Xeon W are ready

December 24, 2017May 25, 2021 David Schor
Samsung 17nm follows Intel 16

Samsung 17nm follows Intel 16

May 22, 2022May 22, 2022 David Schor
Arm Launches the Cortex-M55 and Its MicroNPU Companion, the Ethos-U55

Arm Launches the Cortex-M55 and Its MicroNPU Companion, the Ethos-U55

February 10, 2020May 25, 2021 David Schor
Intel Reveals Initial 9000-Series Coffee Lake SKUs

Intel Reveals Initial 9000-Series Coffee Lake SKUs

July 3, 2018May 25, 2021 David Schor
SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio

SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio

November 17, 2019May 25, 2021 David Schor

Random Tags

2.5D packaging 3 nm 3D packaging 5 nm 7 nm 7nm 10 nm 10nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 Cortex edge computing EMIB EUV FinFET GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel Intel 7 ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

Reincarnating The 6502 Using Flexible TFT Tech For IoT

Reincarnating The 6502 Using Flexible TFT Tech For IoT

May 8, 2022May 8, 2022 David Schor
Radeon RX 5700: Navi and the RDNA Architecture

Radeon RX 5700: Navi and the RDNA Architecture

February 23, 2020May 25, 2021 David Schor
VLSI 2018: Samsung’s 8nm 8LPP, a 10nm extension

VLSI 2018: Samsung’s 8nm 8LPP, a 10nm extension

July 1, 2018May 25, 2021 David Schor
IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects

IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects

February 17, 2018May 25, 2021 David Schor
Mythic Rolls Out M1000-Series Analog AI Accelerators; Raises $70M Along The Way

Mythic Rolls Out M1000-Series Analog AI Accelerators; Raises $70M Along The Way

August 22, 2021August 22, 2021 David Schor
Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512

Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512

December 9, 2019May 25, 2021 David Schor
TSMC 5-Nanometer Update

TSMC 5-Nanometer Update

November 1, 2019May 25, 2021 David Schor

ARM WorldView All

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
Architectures Mobile Processors 

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

June 28, 2022June 28, 2022 David Schor
Arm Unveils Next-Gen Flagship Core: Cortex-X3
Mobile Processors 

Arm Unveils Next-Gen Flagship Core: Cortex-X3

June 28, 2022June 28, 2022 David Schor
Arm Introduces The Cortex-A715
Architectures Mobile Processors 

Arm Introduces The Cortex-A715

June 28, 2022June 29, 2022 David Schor
Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor

About

WikiChip
WikiChip is an independent publisher based in New York. The WikiChip Fuse section publishes chips and semiconductor related news with our main site offering in-depth semiconductor resources and analysis.

WikiChip Links

  • Main Site
  • WikiChip Fuse
  • Newsletter
  • Main Site
  • WikiChip Fuse

Copyright © 2023 WikiChip LLC. All rights reserved.