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Thursday, May 26, 2022
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  • Samsung 17nm follows Intel 16
  • Reincarnating The 6502 Using Flexible TFT Tech For IoT
  • Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC
  • Samsung-Esperanto Concept AI-SSD Prototype
  • EUV State, NXE:3600D, and Pellicle Readiness and Industrialization
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OCP Accelerator Module (OAM)

Interconnects Packaging 

OCP Makes a Push for an Open Chiplet Marketplace

January 4, 2020May 25, 2021 David Schor 2.5D packaging, Advanced Interface Bus (AIB), chiplet, EMIB, interposer, OCP Accelerator Module (OAM), OCP Open Domain-Specific Architecture (ODSA), Open Compute Project (OCP)

Jumping ahead of emerging semiconductor trends, the OCP new Open Domain-Specific Architecture subgroup makes a push for an open and standardized chiplet interface and marketplace.

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Architectures Hot Chips 31 Neural Processors 

A Look At The Habana Inference And Training Neural Processors

December 15, 2019May 25, 2021 David Schor 16nm, AI, Gaudi, Goya, Habana Labs, Hot Chips, Hot Chips 31, inference, neural processors, OCP Accelerator Module (OAM), training

A look at the Habana inference and training neural processors designed for the acceleration of data center workloads.

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Neural Processors Supercomputing 19 

Intel Starts Shipping Initial Nervana NNP Lineup

December 6, 2019May 25, 2021 David Schor AI, inference, Intel, neural processors, NNP, NNP-T, NPP-L, OCP Accelerator Module (OAM), Spring Crest, Spring Hill, Supermicro, training

Intel starts shipping its initial Nervana NNP lineup for both inference and training acceleration with four initial models in three different form factors.

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Architectures Hot Chips 31 Linley Processor Conference Neural Processors 

A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor

November 10, 2019May 25, 2021 David Schor 16FF+, 16nm, AI, bfloat16, Hot Chips, Hot Chips 31, Intel, Linley Processor Conference, Nervana, neural processors, NNP, NNP-T, OCP Accelerator Module (OAM), training

A look at the microarchitecture of Intel Nervana next-generation data center training neural processor, codename Spring Crest.

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Top Six Articles

  • TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node
  • Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
  • The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids
  • TSMC 2021 Foundry Update: Foundry Roadmap
  • Intel Announces 20Å Node: RibbonFET Devices, PowerVia, 2024 Ramp
  • AMD 3D Stacks SRAM Bumplessly

Recent

  • Samsung 17nm follows Intel 16

    Samsung 17nm follows Intel 16

    May 22, 2022May 22, 2022 David Schor
  • Reincarnating The 6502 Using Flexible TFT Tech For IoT

    Reincarnating The 6502 Using Flexible TFT Tech For IoT

    May 8, 2022May 8, 2022 David Schor
  • Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC

    Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC

    February 20, 2022February 21, 2022 David Schor
  • Samsung-Esperanto Concept AI-SSD Prototype

    Samsung-Esperanto Concept AI-SSD Prototype

    November 21, 2021November 21, 2021 David Schor
  • EUV State, NXE:3600D, and Pellicle Readiness and Industrialization

    EUV State, NXE:3600D, and Pellicle Readiness and Industrialization

    November 20, 2021November 20, 2021 David Schor
  • Intel Launches 12th Gen Core Desktop Alder Lake Processors

    Intel Launches 12th Gen Core Desktop Alder Lake Processors

    October 27, 2021November 3, 2021 David Schor

Random Picks

Japan cancels contract, kicks out 4th fastest supercomputer amid fraud charges

Japan cancels contract, kicks out 4th fastest supercomputer amid fraud charges

April 20, 2018May 25, 2021 David Schor
Intel Unveils Foveros Omni And Foveros Direct; Leveraging Hybrid Bonding

Intel Unveils Foveros Omni And Foveros Direct; Leveraging Hybrid Bonding

July 26, 2021July 26, 2021 David Schor
Qualcomm launches the Centriq 2400 server family

Qualcomm launches the Centriq 2400 server family

November 8, 2017May 25, 2021 David Schor
IBM Introduces Next-Gen Z  Mainframe: The z15; Wider Cores, More Cores, More Cache, Still 5.2 GHz

IBM Introduces Next-Gen Z Mainframe: The z15; Wider Cores, More Cores, More Cache, Still 5.2 GHz

September 14, 2019May 25, 2021 David Schor
Qualcomm introduces a new Vision Intelligence Platform

Qualcomm introduces a new Vision Intelligence Platform

April 12, 2018May 25, 2021 Matt Larson

Random Tags

2.5D packaging 3D packaging 5 nm 5nm 7 nm 7nm 10 nm 10nm 12nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 edge computing EMIB EUV FinFET Foveros GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC

Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC

February 20, 2022February 21, 2022 David Schor
IEDM 2017: GlobalFoundries 7nm process; Cobalt, EUV

IEDM 2017: GlobalFoundries 7nm process; Cobalt, EUV

December 21, 2017May 25, 2021 David Schor
Arm Launches New Neoverse N2 and V1 Server CPUs: 1.4x-1.5x IPC, SVE, and ARMv9

Arm Launches New Neoverse N2 and V1 Server CPUs: 1.4x-1.5x IPC, SVE, and ARMv9

April 27, 2021May 23, 2021 David Schor
TSMC Demonstrates A 7nm Arm-Based Chiplet Design for HPC

TSMC Demonstrates A 7nm Arm-Based Chiplet Design for HPC

June 22, 2019May 25, 2021 David Schor
Intel’s Diamond Mesa Bridges The Gap Between ASIC and FPGA

Intel’s Diamond Mesa Bridges The Gap Between ASIC and FPGA

June 13, 2021June 13, 2021 David Schor
NEC Readies 2nd Gen Vector Engine

NEC Readies 2nd Gen Vector Engine

May 15, 2020May 23, 2021 David Schor
DARPA ERI: HIVE and Intel PUMA Graph Processor

DARPA ERI: HIVE and Intel PUMA Graph Processor

August 4, 2019May 25, 2021 David Schor

ARM WorldView All

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor
A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip
IEDM 2020 Interconnects Packaging Subscriber Only Content 

A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

June 11, 2021June 11, 2021 David Schor
Arm Launches New Coherent And SoC Interconnects: CI-700 & NI-700
Architectures Interconnects Network-on-Chip 

Arm Launches New Coherent And SoC Interconnects: CI-700 & NI-700

May 25, 2021May 25, 2021 David Schor
Arm Launches The DSU-110 For New Armv9 CPU Clusters
Architectures Interconnects Mobile Processors 

Arm Launches The DSU-110 For New Armv9 CPU Clusters

May 25, 2021May 25, 2021 David Schor

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