Today, TSMC is announcing that the company’s N7+ which has entered mass production the second quarter of this year is now delivering customer products to the market. N7+ is built on top of TSMC’s highly successful 7-nanometer process but introduces EUV technology on a few critical layers in order to reduce the design complexity.
TSMC is claiming that since it has begun volume production in the second quarter of 2019, it is matching yields to the original N7 process. We have recently covered TSMC’s roadmap which goes into a bit more details on TSMC N7 yield claims. In a press release, the company stated that “EUV tools have reached production maturity, with tool availability reaching target goals for high-volume production, and output power of greater than 250 watts for day-to-day operations.” Currently, TSMC is using the NXE:3400B with a reported power that greater than 250 W (presumably around 275 W) and we take it to mean that the consider the tool production-ready with availability exceeding 90%. Those values are similar to what Anthony Yen from ASML reported earlier this year. The N7+ process is currently used by Huawei for select products and is expected to be leveraged by AMD for their Zen 3 microarchitecture.
Looking a bit further, TSMC will introduce N6 into risk production in the first quarter of 2020 and volume production by the end of the year. N6, like N7+ will improve density by around 20% but will use design rules fully compatible with N7 which is where we expect most customers to migrate to eventually. N6 ramp will coincide with the mass production of the company’s next major node, the 5-nanometer process.
- TSMC 5-Nanometer Update
- TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging
- SEMICON West 2019: ASML EUV Update
- TSMC Demonstrates A 7nm Arm-Based Chiplet Design for HPC
- TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO
- TSMC Announces 6-Nanometer Process
- IBM Chooses Samsung 7nm EUV for Next-Gen POWER and Z Microprocessors
- NEC Refreshes SX-Aurora Vector Engine, Outlines Roadmap
- Japanese AI Startup Preferred Networks Designed A Custom Half-petaFLOPS Training Chip
- Samsung M5 Core Details Show Up
- SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio
- A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip
- Groq Tensor Streaming Processor Delivers 1 PetaOPS of Compute
- Arm Makes Headway In HPC, Cloud
- Intel Announces Keem Bay: 3rd Generation Movidius VPU
- A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor
- Marvell Lays Out ARM Server Roadmap