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Sunday, June 26, 2022
Latest:
  • A Look At Samsung’s 4LPE Process
  • A Look At Intel 4 Process Technology
  • Samsung 17nm follows Intel 16
  • Reincarnating The 6502 Using Flexible TFT Tech For IoT
  • Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC
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CHA

Architectures Neural Processors Server Processors 

Centaur New x86 Server Processor Packs an AI Punch

January 24, 2020May 25, 2021 David Schor 16nm, AI, AVX-512, Centaur Technology, CHA, inference, neural processors, x86

A look at Centaur’s new server-class x86 SoC with an integrated neural processor.

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Architectures Embedded Processors Neural Processors Server Processors 

Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512

December 9, 2019May 25, 2021 David Schor 16nm, AVX-512, Centaur Technology, CHA, inference, neural processors, VIA Technologies, x86

Centaur lifts the veil on CNS, its next-generation x86 core for data center and edge computing. The core improving performance in many areas and adds support for the AVX-512 extension.

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Top Six Articles

  • A Look At Intel 4 Process Technology
  • A Look At Samsung’s 4LPE Process
  • TSMC Details 5 nm
  • IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects
  • TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node
  • TSMC 2021 Foundry Update: Foundry Roadmap

Recent

  • A Look At Samsung’s 4LPE Process

    A Look At Samsung’s 4LPE Process

    June 26, 2022June 26, 2022 David Schor
  • A Look At Intel 4 Process Technology

    A Look At Intel 4 Process Technology

    June 19, 2022June 20, 2022 David Schor
  • Samsung 17nm follows Intel 16

    Samsung 17nm follows Intel 16

    May 22, 2022May 22, 2022 David Schor
  • Reincarnating The 6502 Using Flexible TFT Tech For IoT

    Reincarnating The 6502 Using Flexible TFT Tech For IoT

    May 8, 2022May 8, 2022 David Schor
  • Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC

    Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC

    February 20, 2022February 21, 2022 David Schor
  • Samsung-Esperanto Concept AI-SSD Prototype

    Samsung-Esperanto Concept AI-SSD Prototype

    November 21, 2021November 21, 2021 David Schor

Random Picks

EUV State, NXE:3600D, and Pellicle Readiness and Industrialization

EUV State, NXE:3600D, and Pellicle Readiness and Industrialization

November 20, 2021November 20, 2021 David Schor
AMD 3D Stacks SRAM Bumplessly

AMD 3D Stacks SRAM Bumplessly

June 7, 2021June 7, 2021 David Schor
Intel Discloses 9th Gen Core, Refreshes Core X, And Reintroduces STIM

Intel Discloses 9th Gen Core, Refreshes Core X, And Reintroduces STIM

October 14, 2018May 25, 2021 David Schor
TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter

TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter

April 17, 2020May 25, 2021 David Schor
Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Random Tags

2.5D packaging 3D packaging 5 nm 5nm 7 nm 7nm 10 nm 10nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 AVX-512 chiplet Coffee Lake Core i5 Core i7 Core i9 edge computing EMIB EUV FinFET GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

Ice Lake Brings A New CPU, GPU, IPU, and I/Os, To Follow By Tiger Lake Next Year

Ice Lake Brings A New CPU, GPU, IPU, and I/Os, To Follow By Tiger Lake Next Year

May 12, 2019May 25, 2021 David Schor
TSMC Announces 6-Nanometer Process

TSMC Announces 6-Nanometer Process

April 16, 2019May 25, 2021 David Schor
Intel Expands 22FFL With Production-Ready RRAM and MRAM on FinFET

Intel Expands 22FFL With Production-Ready RRAM and MRAM on FinFET

October 18, 2019May 25, 2021 David Schor
Hot Chips 30: Nvidia Xavier SoC

Hot Chips 30: Nvidia Xavier SoC

September 8, 2018May 25, 2021 David Schor
Arm Launches The DSU-110 For New Armv9 CPU Clusters

Arm Launches The DSU-110 For New Armv9 CPU Clusters

May 25, 2021May 25, 2021 David Schor
TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging

TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging

July 28, 2019May 25, 2021 David Schor
Intel Introduces 2nd Gen Neuromorphic Research Chip: Loihi 2 on Intel 4 EUV Process

Intel Introduces 2nd Gen Neuromorphic Research Chip: Loihi 2 on Intel 4 EUV Process

September 30, 2021September 30, 2021 David Schor

ARM WorldView All

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor
A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip
IEDM 2020 Interconnects Packaging Subscriber Only Content 

A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

June 11, 2021June 11, 2021 David Schor
Arm Launches New Coherent And SoC Interconnects: CI-700 & NI-700
Architectures Interconnects Network-on-Chip 

Arm Launches New Coherent And SoC Interconnects: CI-700 & NI-700

May 25, 2021May 25, 2021 David Schor
Arm Launches The DSU-110 For New Armv9 CPU Clusters
Architectures Interconnects Mobile Processors 

Arm Launches The DSU-110 For New Armv9 CPU Clusters

May 25, 2021May 25, 2021 David Schor

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