In March of this year Intel announced their 22FFL process. At the 63rd IEEE International Electron Devices Meeting (IEDM), Intel presented their highly anticipated paper on this process technology. The paper was presented by Dr. Ben Sell, integration manager at Intel.
While Intel’s regular process technology is geared toward high-performance chips, there is a growing need for a different process that is optimized around a different set of features such as ultra-low power, RF performance, and low design and wafer cost. With those optimizations in mind, Intel developed a new technology called “22 nm FinFET Low Power” or “22FFL” for short. Despite its name, 22FFL borrows more from Intel’s 14nm than it does from their 22nm process. In other words, 22FFL can be thought of as a relaxed 14nm process optimized for mobile and RF applications. “We started with our 14-nanometer transistors and improved from there,” Ben said.
The primary features of Intel’s 22FFL are:
- Low-cost – overall low wafer cost as well as ease of use which lowers designs cost
- High-performance – 14nm transistors were the starting point, adopted for this process
- Ultra-low leakage – special transistors with much lower total leakage than what Intel normally uses for their own technologies
- Low Vmin – Support for low Vmin was needed for reducing the active power
For analog, RF, and I/O functionality 22FFL also features:
- Low noise analog
- High voltage
- High frequency RF
Simplified Metal Stack
For their own products, Intel uses a highly advanced metal stack that offers very tight interconnects that are both complex and expensive to design. 22FFL offers a very simple metal stack with relaxed metal pitches meaning a single-pattern backend flow that reduces cost and is highly flexible and easy to use.
The image above shows the standard 22FFL metallization stack. At the bottom are the transistors on top of which are 6 metal layers with a 90 nm pitch. On top this Intel added two thick metal layers – one with a 1,080 nm pitch and one with a 4-micron pitch. For some applications, adding intermediate layers between the M6 and M7 is very beneficial which is why they offer 2x, 4x, and 8x layers as options.
The two upper layers are designed for global routing. Note that upper-most layer (M8) has a second function – it was specifically designed to be very good for building high-Q inductors (discussed later in this article). Between the M8 and M7, there are the metal-insulator-metal (MIM) capacitors that are used for decoupling the signal capacitance.
Overall, the backend metallization stack is shown below.
|22FFL Backend Metallization|
|M 2x||180 nm||2x option|
|M 4x||360 nm||4x option|
|M 8x||720 nm||8x option|
|M7 12x||1080 nm||12x|
|M8||4000 nm||Thick Metal|