The performance we talked about earlier is for the standard 22FFL devices which had a fin pitch of 108nm. In addition to those devices, Intel introduced 144nm pitch devices for ultra-low leakage. 22FFL ULL devices have sub-1 picoamp per micron total leakage. Those devices provide up to an additional 75x reduction in leakage.
In the graph above, Intel’s original 22nm process (on the upper-left corner) can be used as a reference. The high-performance 22FFL devices start at the very top-right corner. Those six points represent the six devices we mentioned earlier (LP, Nom, HP, LPLVT, LVT, ULVT). There is a range of over 500x between the highest- and lowest- leakage among those devices. The Ultra-low leakage devices can offer an additional 75x reduction in leakage. We believe those are among the lowest, if not the lowest, total leakage logical devices reported with sub 1-picoamp per micron leakage.
We have summarized the three types of logic devices offered by Intel’s 22FFL.
|22FFL Logic Devices|
|High Performance||Low Power||Ultra Low Power|
|Gate Pitch||108 nm||144 nm|
|Fin Pitch||45 nm|
@ 0.70 V
|nMOS||1.24 mA/Î¼m||0.81 mA/Î¼m||0.10 mA/Î¼m|
|pMOS||1.22 mA/Î¼m||0.81 mA/Î¼m||0.10 mA/Î¼m|
|Ioff||10 nA/Î¼m||100 pA/Î¼m||1 pA/Î¼m|
As expected, a number of SRAM bit cells were developed for 22FFL. At their 2017 IEDM presentation Intel reported three cells: high current cell (HCC), high density cell (HDC), and a low leakage cell (HCC-LL). For the HCC SRAM, which is a modified 14nm SRAM, Intel reported a cell area of 0.087 Î¼mÂ² and a low Vmin of 490 mV. The HCC is a slightly bigger cell, reported at 0.107 Î¼mÂ². But if you’re willing to pay for a little bit more area and a bit higher leakage, you get much higher current and even lower Vmin (reported at 440 mV which is actually one of the lowest Vmin reported to date).
The HCC-LL SRAM is based on the ultra-low leakage device with a bit cell leakage of sub-picoamp per bit. Since the Vth is higher for this cell, the Vmin is also higher but has been reported to be around 720 mV. Note that the cell area was not reported.
For the graph above Intel’s figure of merit is at the Vmin at the 95 percentile. Those values were obtained based on 9000 dies of 16 Mib and 32 Mib 6T SRAM arrays at worst case after stress testing.
|Area||0.107 Î¼mÂ²||0.087 Î¼mÂ²||N/R|
|Vmin||440 mV||490 mV||720 mV|
N/R – Not reported
The good logic characteristics also transfer to analog transistors. Intel presented three analog devices. Since the Rout is proportional to the channel length, those three devices have channel lengths of 144nm, 216nm, and 270nm.
For their longest channel length devices with 6 fins Intel reported an Rout of 0.68 MÎ©. In the graph above, the black points are Intel’s previous technologies. They use GM * Rout as a way of comparing the performance of their transistors. The first few red points are actually the logic 22FFL devices which also have a better GM*Rout then their old technologies but for the analog devices with much bigger channel length the improvement is pretty substantial.
At IEDM they presented a PLL which was designed with those analog devices. At 3.2 GHz output frequency and 0.85 volt Intel reported 0.77 mW of power. An almost identical device was actually presented a few years ago at IEDM for their 14nm process. Compared to the PLL device implemented on their 14nm, the 22FFL PLL gets much lower power for roughly the same jitter.