WikiChip Fuse

Ampere Ships First Gen ARM Server Processors

David SchorServer ProcessorsSeptember 19, 2018 Tagged 16FF+, 16nm, Ampere Computing, ARM, ARMv8, Skylark, X-Gene

Partnering up with Lenovo, ARM server startup Ampere has announced their first-generation eMAG microprocessors are now shipping.

Hot Chips 30: Intel Kaby Lake G

David SchorCircuit Design, Hot Chips 30, PackagingSeptember 9, 2018 Tagged 14nm, 2.5D packaging, 3D packaging, AMD, CPU, EMIB, GPU, Intel, Kaby Lake, Kaby Lake G, multi-chip package, Radeon Vega, x86

A look at Intel’s current generation of Thin & Light processors with high-performance graphics, formerly known as Kaby Lake G, from Hot Chips 30.

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Hot Chips 30: Nvidia Xavier SoC

David SchorArchitectures, Floorplanning, Hot Chips 30September 8, 2018 Tagged 12FFN, 12nm, AI, ARM, ARMv8, neural processors, Nvidia, NVLink, Tegra, Xavier

An overview of the Xavier SoC which was detailed by Nvidia at Hot Chips 30.

Hot Chips 30: AMD Raven Ridge

David SchorArchitectures, Circuit Design, Hot Chips 30August 26, 2018 Tagged 14LPP, 14nm, AMD, AMD's infinity fabric, APU, Hot Chips, Hot Chips 30, Radeon Vega, Raven Ridge, Vega, x86, Zen

Overview of AMD Raven Ridge APUs that were recently detailed at Hot Chips 30.

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Cavium Takes ARM to Petascale with Astra

David SchorSupercomputersAugust 25, 2018 Tagged ARM, ARMv8, Cavium, DoE, HPC, Sandia, Supercomputers, ThunderX2, Vulcan

A look at the Astra supercomputer, the most powerful ARM-based supercomputer being built for Sandia National Labs.

AMD Announces Threadripper 2, Chiplets Aid Core Scaling

David SchorDesktop ProcessorsAugust 7, 2018 Tagged 12LP, 12nm, AMD, HEDT, Ryzen, Threadripper, Threadripper 2, x86, Zen

AMD announces their second-generation Threadripper processors with up to 32 cores based on their 12nm Zen+ microarchitecture.

VLSI 2018: Samsung’s 2nd Gen 7nm, EUV Goes HVM

David SchorProcess Technologies, VLSI 2018August 4, 2018 Tagged 7LPP, 7nm, EUV, process technology, Samsung, VLSI 2018, VLSI Symposium

A look at Samsung’s 2nd generation 7nm process that was recently disclosed at the 38th Symposium on VLSI Technology.

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Intel Opens AIB for DARPA’s CHIPS Program as a Royalty-Free Interconnect Standard for Chiplet Architectures

David SchorInterconnectsJuly 24, 2018 Tagged Advanced Interface Bus, AIB, DARPA, EMIB, Intel, interconnects, Packaging

At the DARPA 2018 ERI Summit, Intel announced their contribution of a royalty-free bus standard to DARPA’s CHIPS Program, allowing seamless communication between multiple packaged chiplets.

VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP

David SchorFoundries, Process Technologies, VLSI 2018July 22, 2018 Tagged 12LP, 12nm, 14LPP, 14nm, FinFET, GlobalFoundries, process technology

A look at GlobalFoundries 12nm Leading Performance technology, 12LP, an enhanced 14nm process. The process was recently presented at the 2018 Symposia on VLSI Technology and Circuits.

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Intel Launches Desktop Xeon E, Their Fastest Entry-Level Workstation Processors

David SchorDesktop Processors, Server ProcessorsJuly 13, 2018 Tagged Coffee Lake, Coffee Lake E, Intel, x86, Xeon E, Xeon E3

Intel has launched their fastest entry-level workstation microprocessors based on Coffee Lake.