Your Chips and Semi News
Our latest coverage from the chip architecture world, including announced and planned as well as recently launched products.
Intel launches its 3rd Generation Xeon Scalable, formerly Ice Lake. Fabricated on the company’s 10nm process, those server chips go up to 40 Sunny Cove cores and offer a 20% IPC improvement over the prior generation.
Ten years after launching ARMv8, Arm is launching the ARMv9 architecture for the next decade of compute.
Intel publishes details of its upcoming Advanced Matrix Extension (AMX), an x86 extension set to debut with Sapphire Rapids that introduces a new matrix register file and accompanying matrix operations.
A look at the new Cortex-M55, an embedded ARMv8 core with the new Helium vector extension.
Our latest coverage from the semiconductor world including recent announcements and analysis of new process nodes from semiconductor foundries including Intel, TSMC, Samsung, GlobalFoundries, and other.
A look at ODI, a new family of packaging interconnect technologies that bridges the gap between Intel’s EMIB (2.5D) and Foveros (3D) by providing the flexibility of an EMIB in 3D with additional benefits of thermal & power.
The latest chip-related news from the world of HPC and supercomputers.
A look at ODI, a new family of packaging interconnect technologies that bridges the gap between Intel’s EMIB (2.5D) and Foveros (3D) by providing the flexibility of an EMIB in 3D with additional benefits of thermal & power.
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NEC readies 2nd-generation Vector Engine, Type 20, offering higher memory bandwidth and a few more vector cores.
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TSMC announces its intention to build and operate an advanced 5-nanometer fab in Arizona.
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Intel launches its 10th-generation Comet Lake-based vPro processors.
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Intel launches a new series of Xeon W processors for entry-level workstations based on Comet Lake.
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AMD launches its Zen 2-based Ryzen Pro 4000 series for enterprise customers.
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Intel launches 10th Generation Core desktop processors, formerly codename Comet Lake. The new lineup brings 22 new chips with up to 10 cores and 20 threads with turbo frequencies of up to 5.3 GHz.
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TSMC reports a flat Q1 amid the COVID-19 pandemic, ramps its 5nm node with good yield and discloses key 3-nanometer (N3) details. N3 will be a full node jump over N5 and is expected to offer over a quarter-billion transistors per each millimeter square of silicon.
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Ranovus launches its Odin platform, a multi-wavelength Quantum Dot Laser (QDL) based silicon photonic engine which includes 800Gbps to 3.2Tbps single-chip engines as well as co-packaged optics scaling up to 51.2Tbps for next-generation data center switches and other HPC compute chips that require high bandwidth capacity.
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A look at Lakefield, Intel’s new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company Foveros packaging technology.
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