WikiChip Fuse

Arm Unveils the Cortex-A78: When Less Is More

Architectures May 26, 2020 0

Arm unveils the Cortex-A78 microarchitecture for next-generation flagship smartphones. Read more

Arm Cortex-X1: The First From The Cortex-X Custom Program

Architectures May 26, 2020 0

Arm launches the Cortex-X1, their most powerful Cortex CPU to date. This is the... Read more

IBM Releases Power ISA v3.1; To Present POWER10 At Hot Chips 32

Hot Chips 32 May 23, 2020 0

IBM releases Power ISA v3.1. Among the new instructions, there is new bfloat16 support,... Read more

Left, Right, Above, and Under: Intel 3D Packaging Tech Gains Omnidirectionality

Interconnects May 17, 2020 3

A look at ODI, a new family of packaging interconnect technologies that bridges the... Read more

NEC Readies 2nd Gen Vector Engine

Architectures May 15, 2020 0

NEC readies 2nd-generation Vector Engine, Type 20, offering higher memory bandwidth and a few... Read more
Arm Unveils the Cortex-A78: When Less Is More
Arm unveils the Cortex-A78 microarchitecture for next-generation flagship smartphones.
Arm Cortex-X1: The First From The Cortex-X Custom Program
Arm launches the Cortex-X1, their most powerful Cortex CPU to date. This is the first CPU from the new...
NEC Readies 2nd Gen Vector Engine
NEC readies 2nd-generation Vector Engine, Type 20, offering higher memory bandwidth and a few more vector cores.
A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC
A look at Lakefield, Intel's new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company...
IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache
IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of...
CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor
CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active...
Left, Right, Above, and Under: Intel 3D Packaging Tech Gains Omnidirectionality
A look at ODI, a new family of packaging interconnect technologies that bridges the gap between Intel's EMIB (2.5D)...
TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter
TSMC reports a flat Q1 amid the COVID-19 pandemic, ramps its 5nm node with good yield and discloses key...
TSMC Details 5 nm
TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry's highest density transistors with...
TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications
TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The...
TSMC Digs Trenches In Search Of Higher Performance
TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new,...
UMC Rolls Out 22-Nanometer
UMC says it has started rolling out its 22-nanometer planar process, offering a new lower-power and cost-sensitive migration path...
Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect
A dive into the Rosetta ASIC switch, the engine behind Cray's new Slingshot interconnect powering the upcoming Shasta exascale...
Japanese AI Startup Preferred Networks Designed A Custom Half-petaFLOPS Training Chip
Japanese AI Startup Preferred Networks has been working on a custom training chip with a peak performance of half-petaFLOPS...
SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio
Intel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel's first Xe GPGPU for HPC,...

Conference Coverage

A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC
A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered...
Intel Expands 22FFL With Production-Ready RRAM and MRAM on FinFET
Intel expands its 22FFL process with new production-ready MRAM and RRAM technologies.
TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging
An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.
A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC
A look at Lakefield, Intel's new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company...
TSMC Details 5 nm
TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry's highest density transistors with...
TSMC Digs Trenches In Search Of Higher Performance
TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new,...
A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC
A look at Lakefield, Intel's new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company...
TSMC Details 5 nm
TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry's highest density transistors with...
IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache
IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of...
IBM Releases Power ISA v3.1; To Present POWER10 At Hot Chips 32
IBM releases Power ISA v3.1. Among the new instructions, there is new bfloat16 support, new reduced-precision outer-product operations including...
A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC
A look at Lakefield, Intel's new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company...
Ayar Labs Realizes Co-Packaged Silicon Photonics
Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step...
A Look At The Habana Inference And Training Neural Processors
A look at the Habana inference and training neural processors designed for the acceleration of data center workloads.
A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip
A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI...
A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor
A look at the microarchitecture of Intel Nervana next-generation data center training neural processor, codename Spring Crest.