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  • A Look At AMD’s 3D-Stacked V-Cache
  • IEDM 2022: Did We Just Witness The Death Of SRAM?
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores
  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications
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Server Processors

Architectures Circuit Design ISSCC 2020 Manycore Processors Server Processors 

CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

March 1, 2020May 25, 2021 David Schor 28nm, 65 nm, active interposer, CEA-Leti, chiplet, interconnects, interposer, ISSCC, ISSCC 2020, multi-chip package, STMicroelectronics

CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active interposer die.

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Server Processors 

Intel Refreshes 2nd Gen Xeon Scalable, Slashes Prices

February 27, 2020May 25, 2021 David Schor 14 nm, Cascade Lake, Cascade Lake R, Cascade Lake SP, Intel, Xeon Bronze, Xeon Gold, Xeon Platinum, Xeon Scalable, Xeon Silver

Intel refreshes its second-generation Xeon Scalable lineup mid-cycle with new mainstream dual-socket CPUs, improving the performance-per-dollar by as much as 2x over original SKUs.

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Architectures Neural Processors Server Processors 

Centaur New x86 Server Processor Packs an AI Punch

January 24, 2020May 25, 2021 David Schor 16nm, AI, AVX-512, Centaur Technology, CHA, inference, neural processors, x86

A look at Centaur’s new server-class x86 SoC with an integrated neural processor.

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Desktop Processors Mobile Processors Roadmaps Server Processors 

Zhaoxin Unveiled Next-Generation x86 SoC Plans: 32-Core Servers, Sub-7nm Client Designs

December 12, 2019May 25, 2021 David Schor 16nm, 5 nm, China, DDR5, PCIe 4.0, x86, Zhaoxin

Zhaoxin unveiled plans for two new x86 SoC designs: a high-performance 16-nanometer server chip with up to 32 cores and a separate 7 nm mobile and desktop chip.

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Architectures Embedded Processors Neural Processors Server Processors 

Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512

December 9, 2019May 25, 2021 David Schor 16nm, AVX-512, Centaur Technology, CHA, inference, neural processors, VIA Technologies, x86

Centaur lifts the veil on CNS, its next-generation x86 core for data center and edge computing. The core improving performance in many areas and adds support for the AVX-512 extension.

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Roadmaps Server Processors Supercomputing 19 Vector Processors 

NEC Refreshes SX-Aurora Vector Engine, Outlines Roadmap

November 30, 2019May 25, 2021 David Schor NEC, SX series, SX-Aurora, Vector Engine (VE), vector processors

NEC refreshes its SX-Aurora Vector Engine accelerator cards, adopts AMD processors, and outlines roadmap.

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Architectures Roadmaps Server Processors Supercomputers Supercomputing 19 

SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio

November 17, 2019May 25, 2021 David Schor 10 nm, 7 nm, Aurora, Intel, Sapphire Rapids, Supercomputer, Supercomputers, x86, Xe

Intel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel’s first Xe GPGPU for HPC, 7nm Ponte Vecchio.

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Server Processors 

Arm Makes Headway In HPC, Cloud

November 13, 2019May 25, 2021 David Schor ARM, Azure, Cray, exascale, Fujitsu, Marvell, Scalable Vector Extension (SVE), ThunderX, ThunderX2

Arm makes headway in HPC and cloud with Cray’s new support for the Fujitsu A64FX and Microsoft deployment of Marvell’s ThunderX2 processors.

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Roadmaps Server Processors 

Marvell Lays Out ARM Server Roadmap

November 9, 2019May 25, 2021 David Schor 16nm, 7 nm, ARM, Linley Processor Conference, Marvell, Scalable Vector Extension (SVE), ThunderX, ThunderX2, ThunderX3, ThunderX4

Marvell outlines its current and future Arm server microprocessor roadmap, aiming at a 2-year cadence with greater than 2x performance gen-over-gen.

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Desktop Processors Server Processors 

AMD Announces 3rd Gen Ryzen Threadripper

November 8, 2019May 25, 2021 David Schor 7 nm, AMD, Ryzen Threadripper, x86, Zen 2

AMD announces 3rd-generation Ryzen Threadripper microprocessors with up to 32 cores.

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  • ← Previous
  • Next →

Top Six Articles

  • A Look At Intel 4 Process Technology
  • TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node
  • Arm Introduces Its Confidential Compute Architecture
  • Arm Introduces The Cortex-A715
  • Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
  • IEDM 2022: Did We Just Witness The Death Of SRAM?

Recent

  • A Look At AMD’s 3D-Stacked V-Cache

    A Look At AMD’s 3D-Stacked V-Cache

    December 27, 2022December 27, 2022 David Schor
  • IEDM 2022: Did We Just Witness The Death Of SRAM?

    IEDM 2022: Did We Just Witness The Death Of SRAM?

    December 14, 2022December 15, 2022 David Schor
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    November 1, 2022November 2, 2022 David Schor
  • Intel, SiFive Demo High-Performance  RISC-V Horse Creek Dev Platform On Intel 4 Process

    Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process

    October 7, 2022October 7, 2022 David Schor
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    October 4, 2022October 4, 2022 David Schor
  • Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    October 1, 2022October 3, 2022 David Schor

Random Picks

Intel Stratix 10 DX Adds PCIe Gen 4.0, Cache Coherency: UPI As Stopgap

Intel Stratix 10 DX Adds PCIe Gen 4.0, Cache Coherency: UPI As Stopgap

September 20, 2019May 25, 2021 David Schor
AMD introduces Ryzen 2nd Gen up for pre-order

AMD introduces Ryzen 2nd Gen up for pre-order

April 13, 2018May 25, 2021 David Schor
Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Intel Unveils Foveros Omni And Foveros Direct; Leveraging Hybrid Bonding

Intel Unveils Foveros Omni And Foveros Direct; Leveraging Hybrid Bonding

July 26, 2021July 26, 2021 David Schor
TSMC Digs Trenches In Search Of Higher Performance

TSMC Digs Trenches In Search Of Higher Performance

December 14, 2019May 25, 2021 David Schor

Random Tags

2.5D packaging 3 nm 3D packaging 5 nm 7 nm 7nm 10 nm 10nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 Cortex edge computing EMIB EUV FinFET GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel Intel 7 ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node

TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node

October 26, 2021October 26, 2021 David Schor
Nantero’s NRAM, A Universal Memory Candidate?

Nantero’s NRAM, A Universal Memory Candidate?

September 22, 2018May 25, 2021 David Schor
TSMC Digs Trenches In Search Of Higher Performance

TSMC Digs Trenches In Search Of Higher Performance

December 14, 2019May 25, 2021 David Schor
AMD Announces Threadripper 2, Chiplets Aid Core Scaling

AMD Announces Threadripper 2, Chiplets Aid Core Scaling

August 7, 2018May 25, 2021 David Schor

IBM Open Sources Power ISA, Delays POWER10 to 2021

September 12, 2019May 25, 2021 David Schor
Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

December 22, 2018May 25, 2021 David Schor
WikiChip Fuse Moves to a Decaying Paywall Model

WikiChip Fuse Moves to a Decaying Paywall Model

May 13, 2021May 23, 2021 David Schor

ARM WorldView All

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
Architectures Mobile Processors 

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

June 28, 2022June 28, 2022 David Schor
Arm Unveils Next-Gen Flagship Core: Cortex-X3
Mobile Processors 

Arm Unveils Next-Gen Flagship Core: Cortex-X3

June 28, 2022June 28, 2022 David Schor
Arm Introduces The Cortex-A715
Architectures Mobile Processors 

Arm Introduces The Cortex-A715

June 28, 2022June 29, 2022 David Schor
Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor

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