CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor
CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active interposer die.
Read moreCEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active interposer die.
Read moreIntel refreshes its second-generation Xeon Scalable lineup mid-cycle with new mainstream dual-socket CPUs, improving the performance-per-dollar by as much as 2x over original SKUs.
Read moreA look at Centaur’s new server-class x86 SoC with an integrated neural processor.
Read moreZhaoxin unveiled plans for two new x86 SoC designs: a high-performance 16-nanometer server chip with up to 32 cores and a separate 7 nm mobile and desktop chip.
Read moreCentaur lifts the veil on CNS, its next-generation x86 core for data center and edge computing. The core improving performance in many areas and adds support for the AVX-512 extension.
Read moreNEC refreshes its SX-Aurora Vector Engine accelerator cards, adopts AMD processors, and outlines roadmap.
Read moreIntel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel’s first Xe GPGPU for HPC, 7nm Ponte Vecchio.
Read moreArm makes headway in HPC and cloud with Cray’s new support for the Fujitsu A64FX and Microsoft deployment of Marvell’s ThunderX2 processors.
Read moreMarvell outlines its current and future Arm server microprocessor roadmap, aiming at a 2-year cadence with greater than 2x performance gen-over-gen.
Read moreAMD announces 3rd-generation Ryzen Threadripper microprocessors with up to 32 cores.
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