Skip to content
Thursday, September 29, 2022
Latest:
  • SiFive Introduces A New Coprocessor Interface, Targets Custom Accelerators
  • N3E Replaces N3; Comes In Many Flavors
  • Samsung Foundry On EUV, Pellicles, Capacity, and Yield
  • Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements
  • Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
WikiChip Fuse

WikiChip Fuse

Your Chips and Semi News

  • Home
  • Account
  • Main Site
  • Architectures
    • x86
    • ARM
    • RISC-V
    • Power ISA
    • MIPS
  • Supercomputers
  • 14 nm
  • 12nm
  • 10nm
  • 7nm
  • 5nm

Video Coding Unit (VCU)

Architectures Data Processing Unit Subscriber Only Content 

YouTube Accelerates Transcoding

August 21, 2021August 21, 2021 David Schor accelerator, ASPLOS 2021, google, H.264, subscriber only (general), video acceleration, Video Coding Unit (VCU), VP9, YouTube

Google accelerates YouTube and other video services with custom silicon.

Read more

Top Six Articles

  • N3E Replaces N3; Comes In Many Flavors
  • SiFive Introduces A New Coprocessor Interface, Targets Custom Accelerators
  • A Look At Intel 4 Process Technology
  • Arm Unveils the Cortex-A78: When Less Is More
  • AMD 3D Stacks SRAM Bumplessly
  • Arm Introduces The Cortex-A715

Recent

  • SiFive Introduces A New Coprocessor Interface, Targets Custom Accelerators

    SiFive Introduces A New Coprocessor Interface, Targets Custom Accelerators

    September 20, 2022September 20, 2022 David Schor
  • N3E Replaces N3; Comes In Many Flavors

    N3E Replaces N3; Comes In Many Flavors

    September 4, 2022September 4, 2022 David Schor
  • Samsung Foundry On EUV, Pellicles, Capacity, and Yield

    Samsung Foundry On EUV, Pellicles, Capacity, and Yield

    July 25, 2022July 25, 2022 David Schor
  • Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements

    Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements

    July 5, 2022July 5, 2022 David Schor
  • Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

    Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

    June 28, 2022June 28, 2022 David Schor
  • Arm Unveils Next-Gen Flagship Core: Cortex-X3

    Arm Unveils Next-Gen Flagship Core: Cortex-X3

    June 28, 2022June 28, 2022 David Schor

Random Picks

Esperanto exits stealth mode, aims at AI with a 4,096-core 7nm RISC-V monster

Esperanto exits stealth mode, aims at AI with a 4,096-core 7nm RISC-V monster

January 1, 2018May 25, 2021 David Schor
Intel discloses Tremont, a Goldmont Plus successor

Intel discloses Tremont, a Goldmont Plus successor

April 4, 2018May 25, 2021 David Schor
Q1 2021 Foundry Update: Spending Bonanza

Q1 2021 Foundry Update: Spending Bonanza

May 18, 2021May 23, 2021 David Schor
Huawei Expands Kunpeng Server CPUs, Plans SMT, SVE For Next Gen

Huawei Expands Kunpeng Server CPUs, Plans SMT, SVE For Next Gen

May 3, 2019May 25, 2021 David Schor
Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements

Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements

July 5, 2022July 5, 2022 David Schor

Random Tags

2.5D packaging 3 nm 3D packaging 5 nm 5nm 7 nm 7nm 10 nm 10nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 Cortex edge computing EMIB EUV FinFET GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor

A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor

November 10, 2019May 25, 2021 David Schor
VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP

VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP

July 22, 2018May 25, 2021 David Schor
Intel Stratix 10 DX Adds PCIe Gen 4.0, Cache Coherency: UPI As Stopgap

Intel Stratix 10 DX Adds PCIe Gen 4.0, Cache Coherency: UPI As Stopgap

September 20, 2019May 25, 2021 David Schor
Samsung Discloses Exynos M4 Changes, Upgrades Support for ARMv8.2, Rearranges The Back-End

Samsung Discloses Exynos M4 Changes, Upgrades Support for ARMv8.2, Rearranges The Back-End

January 14, 2019May 25, 2021 David Schor
Arm Ethos is for Ubiquitous AI At the Edge

Arm Ethos is for Ubiquitous AI At the Edge

February 6, 2020May 25, 2021 David Schor
Intel Pushes Out Flagship Premium Tiger Lake Mobile Chips

Intel Pushes Out Flagship Premium Tiger Lake Mobile Chips

May 13, 2021May 23, 2021 David Schor
POWER9 Scales Up To 1.2 TB/s of I/O, Targets NVLink 3, OpenCAPI Memory for 2019

POWER9 Scales Up To 1.2 TB/s of I/O, Targets NVLink 3, OpenCAPI Memory for 2019

October 7, 2018May 25, 2021 David Schor

ARM WorldView All

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
Architectures Mobile Processors 

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

June 28, 2022June 28, 2022 David Schor
Arm Unveils Next-Gen Flagship Core: Cortex-X3
Mobile Processors 

Arm Unveils Next-Gen Flagship Core: Cortex-X3

June 28, 2022June 28, 2022 David Schor
Arm Introduces The Cortex-A715
Architectures Mobile Processors 

Arm Introduces The Cortex-A715

June 28, 2022June 29, 2022 David Schor
Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor

About

WikiChip
WikiChip is an independent publisher based in New York. The WikiChip Fuse section publishes chips and semiconductor related news with our main site offering in-depth semiconductor resources and analysis.

WikiChip Links

  • Main Site
  • WikiChip Fuse
  • Newsletter
  • Main Site
  • WikiChip Fuse

Copyright © 2022 WikiChip LLC. All rights reserved.