CMOS image sensor

IEDM 2017

IEDM 2017: Sony’s 3-layer stacked CMOS image sensor technology

February 3, 2018May 25, 2021 David Schor 3D packaging, CIS, CMOS image sensor, die stacking, IEDM, IEDM 2017, Sony, TSV

At the 2017 IEDM Sony presented their 3-layer stacked state-of-the-art CMOS image sensor (CIS) technology used to minimize rolling shutter distortions and greatly increase the read speed and thus fps through the use of DRAM for temporarily storing the pixel data.