WikiChip Fuse
A look at Samsung’s 2nd generation 7nm process that was recently disclosed at the 38th Symposium on VLSI Technology. VLSI 2018: Samsung’s 2nd Gen 7nm, EUV Goes HVM

Overview

Starting around 2004, the industry slowly switched to 193 nm lithography. But the critical feature sizes have long dropped below this wavelength. To pattern such small features, the industry employed a slew of lithography tricks such as optical proximity correction, double patterning, and even quad patterning.

Lithography Scaling (WikiChip)

Samsung has been using a double patterning technique known as Litho-Etch-Litho-Etch (LELE) once features dropped below the wavelength limits. Recently, for their 10nm technology, they dropped under the double patterning limit forcing them to use triple patterning (Litho-Etch-Litho-Etch-Litho-Etch or LELELE). Finally, at this conference, Samsung unveiled their 8nm which pushes patterning further to LELELELE (Quad).

 

Samsung Patterning (WikiChip)

Under LELE you start out with a substrate, the device layer, and the hardmask. The layer is then split into two masks. Suppose we want to achive a minimal metal pitch of 64nm (similar to Samsung’s 10nm).

WikiChip’s diagram of Starting structure

We would then apply the photoresist and expose it to light over a mask in order to get the desired pattern. Since our desired minimal metal pitch is 64nm, we can start with a 128nm pattern pitch.

WikiChip diagram of the photoresist application.

We then transfer the pattern onto the hardmask which will be used for subsequent steps serving as an ad hoc mask.

WikiChip’s diagram of the etch step in LELE.

Now we can shift the pattern and repeat the process with another set of patterns and photoresist using the same 128nm pattern pitch.

 
 

WikiChip diagram of the second Litho step with a new set of lines and photoresist

We finally use the hardmask and resist as an etch mask for the underlying device layer.

WikiChip’s diagram of the final etching step.

Following the second etch we’re left with the desired pattern where the minimum pitch is achieved is the desired 64nm for this process. This technique has been extended by Samsung for LELELE and LELELELE though the addition of another litho and another etching step allowing them to go to sub-44nm pitches.


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Terry
Terry
1 year ago

Thanks for the updates! I also love the fact 8nm is pretty close!

Fred Chen
Fred Chen
1 year ago

If Samsung used EUV for fin patterning, it seems it should be highlighted by Samsung as a first-time achievement. But it seems only BEOL and MOL were specifically highlighted, just based on the paper.

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