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Latest:
  • A Look At AMD’s 3D-Stacked V-Cache
  • IEDM 2022: Did We Just Witness The Death Of SRAM?
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores
  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications
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8nm

Process Technologies VLSI 2018 

VLSI 2018: Samsung’s 8nm 8LPP, a 10nm extension

July 1, 2018May 25, 2021 David Schor 10LPE, 10LPP, 10nm, 8LPP, 8nm, FinFET, Samsung, VLSI 2018, VLSI Symposium

A look at Samsung’s 8nm 8LPP process that was recently disclosed at the 38th Symposium on VLSI Technology.

Read more
Process Technologies 

Samsung 2nd gen 10nm enters HVM, S3 fab ready for primetime

November 29, 2017May 25, 2021 David Schor 10LPP, 10nm, 7LPP, 7nm, 8LPP, 8nm, EUV, Samsung

Samsung has announced that its 2nd generation 10nm process has entered mass production. The company also announced that their S3-Line fab in South Korea is ready to ramp up production.

Read more

Top Six Articles

  • A Look At Intel 4 Process Technology
  • A Look At AMD’s 3D-Stacked V-Cache
  • TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO
  • Intel 2021 Process Technology Update: Intel 7, Intel 4, Intel 3, and Intel 20A
  • IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery
  • Intel Unveils Foveros Omni And Foveros Direct; Leveraging Hybrid Bonding

Recent

  • A Look At AMD’s 3D-Stacked V-Cache

    A Look At AMD’s 3D-Stacked V-Cache

    December 27, 2022December 27, 2022 David Schor
  • IEDM 2022: Did We Just Witness The Death Of SRAM?

    IEDM 2022: Did We Just Witness The Death Of SRAM?

    December 14, 2022December 15, 2022 David Schor
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    November 1, 2022November 2, 2022 David Schor
  • Intel, SiFive Demo High-Performance  RISC-V Horse Creek Dev Platform On Intel 4 Process

    Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process

    October 7, 2022October 7, 2022 David Schor
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    October 4, 2022October 4, 2022 David Schor
  • Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    October 1, 2022October 3, 2022 David Schor

Random Picks

Samsung 3nm GAA Inches Towards Productization With SRAM, SoC Test Vehicles

Samsung 3nm GAA Inches Towards Productization With SRAM, SoC Test Vehicles

July 8, 2021July 8, 2021 David Schor
Intel 2021 Process Technology Update: Intel 7, Intel 4, Intel 3, and Intel 20A

Intel 2021 Process Technology Update: Intel 7, Intel 4, Intel 3, and Intel 20A

July 26, 2021July 26, 2021 David Schor
A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

June 11, 2021June 11, 2021 David Schor
The Mesh Network For Next-Generation Neoverse Chips

The Mesh Network For Next-Generation Neoverse Chips

May 22, 2021May 23, 2021 David Schor
IEDM 2022: Did We Just Witness The Death Of SRAM?

IEDM 2022: Did We Just Witness The Death Of SRAM?

December 14, 2022December 15, 2022 David Schor

Random Tags

2.5D packaging 3 nm 3D packaging 5 nm 7 nm 7nm 10 nm 10nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 Cortex edge computing EMIB EUV FinFET GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel Intel 7 ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP

VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP

July 22, 2018May 25, 2021 David Schor
Arm’s New Cortex-M55 Breathes Helium

Arm’s New Cortex-M55 Breathes Helium

June 20, 2020May 23, 2021 David Schor
Intel Announces 10th Gen Core Processors Based On 10nm Ice Lake, Now Shipping

Intel Announces 10th Gen Core Processors Based On 10nm Ice Lake, Now Shipping

May 28, 2019May 25, 2021 David Schor
Ranovus Odin: Co-Packaging Next-Gen DC Switches and Accelerators With Silicon Photonics

Ranovus Odin: Co-Packaging Next-Gen DC Switches and Accelerators With Silicon Photonics

April 11, 2020May 25, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor
Intel Rolls Out Cascade Lake Xeon W Processors

Intel Rolls Out Cascade Lake Xeon W Processors

June 3, 2019May 25, 2021 David Schor
IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

January 6, 2019May 25, 2021 David Schor

ARM WorldView All

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
Architectures Mobile Processors 

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

June 28, 2022June 28, 2022 David Schor
Arm Unveils Next-Gen Flagship Core: Cortex-X3
Mobile Processors 

Arm Unveils Next-Gen Flagship Core: Cortex-X3

June 28, 2022June 28, 2022 David Schor
Arm Introduces The Cortex-A715
Architectures Mobile Processors 

Arm Introduces The Cortex-A715

June 28, 2022June 29, 2022 David Schor
Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor

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