ERI Summit 2019

Architectures Circuit Design ERI Summit 2019 FPGAs

DARPA ERI: How Ayar Labs Collaboration With GF Produces A Photonics Chiplet That Can Supercharge Intel FPGAs

July 20, 2019May 25, 2021 David Schor 45 nm, 45RFSOI, Advanced Interface Bus (AIB), Ayar Labs, chiplet, DARPA, EMIB, ERI Summit, ERI Summit 2019, FPGA, GlobalFoundries, Photonics, RISC-V, Stratix 10

From a DARPA vision and a $15 million seed to a commercialized CMOS silicon photonics product: how Ayar Labs collaboration with GF produces a photonics chiplet that can supercharge Intel FPGAs.

ERI Summit 2019

DARPA ERI: HIVE and Intel PUMA Graph Processor

DARPA ERI: How Ayar Labs Collaboration With GF Produces A Photonics Chiplet That Can Supercharge Intel FPGAs

Intel Labs Builds A Neuromorphic System With 64 To 768 Loihi Chips: 8 Million To 100 Million Neurons