IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects

A Search For A Better Density Metric

Quantifying density advantages is getting complicated. Up until very recent nodes, standard cells came in mostly similar designs. This allowed a relatively simple way of comparing densities. The oldest and perhaps still the most popular way of comparing densities is the CPPxMMx Metric. Using this method, you can simply plot the process contacted gate (poly) pitch times the metal pitch of the various processes.

WikiChip’s Process Comparison using the CPP x MMx Metric. Drawn to scale.
Basic Geometry Is Not Enough

As transistors scaled down further with FinFET it became possible to very effectively increase drive current by increasing the fin height while reducing the pitch. With high enough drive current it became possible to perform fin depopulation – i.e. eliminating fins which enables metal tracks reduction, lowers the dynamic power, while still preserving speed or even increasing it through clever optimizations.


WikiChip’s Diagram showing fin depopulation and fin pitch reduction along with tracks reduction.

When foundries started reducing tracks, the old CPP x MMP Metric fell apart as it fails to capture the height of the cells that have been reduced. To compensate for this, the old metric was retrofitted to account for the difference in tracks between processes – CPP x MMP x Tracks.

Doesn’t Cover Width

As scaling continues, new innovative ways for extracting additional density is being introduced. For example COAG further reduces the cell height while using a single dummy further reduces the cell width.

Impact On Cell Density
Affects the Height Affects the Width
Metal pitch
Number of tracks
Gate pitch

Since neither the width reductions nor the height reductions can be captured by even the modified metric, Mark Bohr proposed a new metric altogether:

Intel’s MTr/mm² Equation

Supposedly it’s actually not a new metric, it simply got resurrected by Intel, albeit we’ve never heard of it. Nonetheless, the metric is a very interesting one because it successfully captures the effects of basic scaling (i.e., CPP x MMP) as well as the reduction in tracks. Additionally, since the equation relies on gate density, it also takes into account other cell optimizations that affect the cell width. The metric uses two common standard cells: 2-input NAND gate which consists of just four transistors and a fairly large scan flip-flop cell.


The total density is then a weighted sum of the average contribution of cell to the overall area. The total density consists of 60% that of the small logic cell and 40% of the complex cell.

WikiChip’s visual of a small cell (NAND2) and large complex cell (scan flip-flop)

For example, for Intel’s 10nm there are 8 diffusion lines with a fin pitch of 34nm giving us a cell height of 272. With a poly pitch is 54nm, we get [4 transistors] / [272 nm x (3 * 54 nm)] = 90.78 MTr/mm² for the NAND2 gate. For the complex flip-flop, Intel’s optimizations results in around 121 MTr/mm². The total density is thus around 102.9 MTr/mm² (note that Intel reported 100.8 MTr/mm²).

It’s worth noting that even this is insufficient to quantify the density of the process because of the cache. SRAM cells rely largely on just four metal wires: ground, power, WL, and BL. This means none of the standard density metrics can properly capture that area. What this means in practice is that a chip where the cache makes up a much larger portion of the die tends to inflate the transistor density far beyond what the MTr/mm² reports. To solve this Bohr requires that the SRAM bitcell sizes should be reported along with the MTr/mm² density value for a proper comparison.

For a discussion on how it stacks against GF’s 7nm, see the “Some Math” section here. Since large and complex logic makes up a large portion of Intel’s die, the high logic density will definitely benefit them. However, for chips with large caches, Intel is considerably behind the foundries with their solution. Overall, all the leading edge solutions are similar density-wise.

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Maynard Handley
Maynard Handley
3 years ago

Nice article as usual, David, But might I suggest that in most places you replace “resistivity” with “resistance”?

The issue is not “resistivity” per se, no?
The issue is that what matters is the resistance of “wires as manufactured”. This resistance is a composite of bulk resistivity, surface effects, and the effective area that can be dedicated to the wire given manufacturing realities. Use of cobalt lowers the resistance because even though the bulk resistivity goes up, the other factors in that composite go down — the surface effects and the reduced effective area.

James L
James L
Reply to  Maynard Handley
3 years ago

“The issue is not “resistivity” per se, no?”

The issue is both resistance and resistivity though. Resistivity is an intrinsic property which is meant to describe the natural resistance to the flow in unconstrained space. But as you scale, you are no longer in unconstrained space and the increased surface scattering is said to affect the resistivity of the material.

I can’t speak for the author but as someone who discussed the subject with engineers in the past, often when they refer to the resistivity of the wire, it is a simple way of referring to the resistivty of the composite wire (core/barrier as a single material) rather than the resistance which is a function of the length and cross-sectional area.

Sanne Deijkers
Sanne Deijkers
2 months ago

Hi, very nice article which really give insight in the pros and cons of copper versus cobalt. I was however wondering where the following claim comes from: “Additionally, in contrast to copper, it has been demonstrated that a single film, as thin as 1 nm, is sufficient to serve as both the liner and barrier for cobalt.”

I would be very interested to learn more about the difference in barrier requirements for the use of copper and cobalt.

Would love your thoughts, please comment.x

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