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Latest:
  • A Look At AMD’s 3D-Stacked V-Cache
  • IEDM 2022: Did We Just Witness The Death Of SRAM?
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores
  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications
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exascale

Server Processors 

Arm Makes Headway In HPC, Cloud

November 13, 2019May 25, 2021 David Schor ARM, Azure, Cray, exascale, Fujitsu, Marvell, Scalable Vector Extension (SVE), ThunderX, ThunderX2

Arm makes headway in HPC and cloud with Cray’s new support for the Fujitsu A64FX and Microsoft deployment of Marvell’s ThunderX2 processors.

Read more
Supercomputers 

Intel axes Knights Hill, plans a new microarchitecture for exascale

November 14, 2017May 25, 2021 David Schor 10nm, Aurora, Cray, DoE, exascale, Intel, x86

In preparation for the United States’ first exascale supercomputer, Intel announces they are cancelling next-generation Xeon Phi processors (codename Knights Hill) in favor of a brand new platform and microarchitecture specifically designed for exascale.

Read more

Top Six Articles

  • A Look At Intel 4 Process Technology
  • TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node
  • Arm Introduces Its Confidential Compute Architecture
  • Arm Introduces The Cortex-A715
  • N3E Replaces N3; Comes In Many Flavors
  • Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

Recent

  • A Look At AMD’s 3D-Stacked V-Cache

    A Look At AMD’s 3D-Stacked V-Cache

    December 27, 2022December 27, 2022 David Schor
  • IEDM 2022: Did We Just Witness The Death Of SRAM?

    IEDM 2022: Did We Just Witness The Death Of SRAM?

    December 14, 2022December 15, 2022 David Schor
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    November 1, 2022November 2, 2022 David Schor
  • Intel, SiFive Demo High-Performance  RISC-V Horse Creek Dev Platform On Intel 4 Process

    Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process

    October 7, 2022October 7, 2022 David Schor
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    October 4, 2022October 4, 2022 David Schor
  • Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    October 1, 2022October 3, 2022 David Schor

Random Picks

AMD launches EPYC Embedded 3000 and Ryzen Embedded V1000 SoCs

AMD launches EPYC Embedded 3000 and Ryzen Embedded V1000 SoCs

February 23, 2018May 25, 2021 David Schor
Intel Launches Desktop Xeon E, Their Fastest Entry-Level Workstation Processors

Intel Launches Desktop Xeon E, Their Fastest Entry-Level Workstation Processors

July 13, 2018May 25, 2021 David Schor
Intel Launches Lakefield: An Experiment With Multiple New Technologies

Intel Launches Lakefield: An Experiment With Multiple New Technologies

June 15, 2020May 23, 2021 David Schor
Samsung-Esperanto Concept AI-SSD Prototype

Samsung-Esperanto Concept AI-SSD Prototype

November 21, 2021November 21, 2021 David Schor
Samsung Ramps 7nm, Preps 5nm, And Adds 6nm

Samsung Ramps 7nm, Preps 5nm, And Adds 6nm

April 16, 2019May 25, 2021 David Schor

Random Tags

2.5D packaging 3 nm 3D packaging 5 nm 7 nm 7nm 10 nm 10nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 Cortex edge computing EMIB EUV FinFET GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel Intel 7 ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

Intel Sunny Cove Core To Deliver A Major Improvement In Single-Thread Performance, Bigger Improvements To Follow

Intel Sunny Cove Core To Deliver A Major Improvement In Single-Thread Performance, Bigger Improvements To Follow

May 28, 2019May 25, 2021 David Schor
ISSCC 2018: AMD’s Zeppelin; Multi-chip routing and packaging

ISSCC 2018: AMD’s Zeppelin; Multi-chip routing and packaging

March 24, 2018May 25, 2021 David Schor
Arm Announces a New Security Certification Program for IoT Devices

Arm Announces a New Security Certification Program for IoT Devices

February 25, 2019May 25, 2021 David Schor
ASML Q4: NXE:3400C Machines Ramp; Strong Growth Due to EUV in 2020

ASML Q4: NXE:3400C Machines Ramp; Strong Growth Due to EUV in 2020

January 22, 2020May 25, 2021 David Schor
Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512

Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512

December 9, 2019May 25, 2021 David Schor
X-Gene 3 gets a second chance at Ampere with a new 32-core 16nm ARM processor

X-Gene 3 gets a second chance at Ampere with a new 32-core 16nm ARM processor

February 5, 2018May 25, 2021 David Schor
Intel axes Knights Hill, plans a new microarchitecture for exascale

Intel axes Knights Hill, plans a new microarchitecture for exascale

November 14, 2017May 25, 2021 David Schor

ARM WorldView All

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
Architectures Mobile Processors 

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

June 28, 2022June 28, 2022 David Schor
Arm Unveils Next-Gen Flagship Core: Cortex-X3
Mobile Processors 

Arm Unveils Next-Gen Flagship Core: Cortex-X3

June 28, 2022June 28, 2022 David Schor
Arm Introduces The Cortex-A715
Architectures Mobile Processors 

Arm Introduces The Cortex-A715

June 28, 2022June 29, 2022 David Schor
Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor

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