SiFive Introduces A New Coprocessor Interface, Targets Custom Accelerators
SiFive introduces a new high-performance coprocessor interface targeting custom accelerators; scores design wins from Google, NASA.
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AI
The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids
Intel publishes details of its upcoming Advanced Matrix Extension (AMX), an x86 extension set to debut with Sapphire Rapids that introduces a new matrix register file and accompanying matrix operations.
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Arm’s New Cortex-M55 Breathes Helium
A look at the new Cortex-M55, an embedded ARMv8 core with the new Helium vector extension.
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Arm Ethos is for Ubiquitous AI At the Edge
Arm’s Ethos family takes aim at ubiquitous AI with NPUs for ultra-low power IoT to high-performance smartphones and AR/VR.
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Intel Axes Nervana Just Two Months After Launch
Intel axes Nervana in favor of Habana.
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Centaur New x86 Server Processor Packs an AI Punch
A look at Centaur’s new server-class x86 SoC with an integrated neural processor.
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A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC
A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered accelerator.
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A Look At The Habana Inference And Training Neural Processors
A look at the Habana inference and training neural processors designed for the acceleration of data center workloads.
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Intel Starts Shipping Initial Nervana NNP Lineup
Intel starts shipping its initial Nervana NNP lineup for both inference and training acceleration with four initial models in three different form factors.
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Japanese AI Startup Preferred Networks Designed A Custom Half-petaFLOPS Training Chip
Japanese AI Startup Preferred Networks has been working on a custom training chip with a peak performance of half-petaFLOPS as well as a supercomputer with a peak performance of 2 exaFLOPS (HP).
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