EUV – Page 2 – WikiChip Fuse

Samsung 7nm Enters Risk Production, Talks Roadmap, Scaling Boosters, and the ARM Ecosystem

October 28, 2018May 25, 2021 David Schor 2.5D packaging, 3D packaging, 3GAAE, 3GAAP, 3GAE, 3nm, 4LPE, 4LPP, 5LPE, 5nm, 7LPP, 7nm, EUV, Packaging, Samsung

Samsung gives an update on their 7nm EUV-based process, details the foundry technology roadmap down to 3nm and the ARM ecosystem that follows.

Process Technologies VLSI 2018

VLSI 2018: Samsung’s 2nd Gen 7nm, EUV Goes HVM

August 4, 2018May 25, 2021 David Schor 7LPP, 7nm, EUV, process technology, Samsung, VLSI 2018, VLSI Symposium

A look at Samsungâ€™s 2nd generation 7nm process that was recently disclosed at the 38th Symposium on VLSI Technology.

IEDM 2017 Process Technologies

IEDM 2017: GlobalFoundries 7nm process; Cobalt, EUV

December 21, 2017May 25, 2021 David Schor 7LP, 7nm, AMD, EUV, FinFET, GlobalFoundries, IBM, IEDM, IEDM 2017, process technology, SADP, SAQP

At the 2017 IEDM GlobalFoundries detailed their 7nm Leading Performance (7LP) process, an aggressively scaled version of their 14nm process optimized for next-generation mobile, SoC, and high-performance applications.

Process Technologies

Samsung 2nd gen 10nm enters HVM, S3 fab ready for primetime

November 29, 2017May 25, 2021 David Schor 10LPP, 10nm, 7LPP, 7nm, 8LPP, 8nm, EUV, Samsung

Samsung has announced that its 2nd generation 10nm process has entered mass production. The company also announced that their S3-Line fab in South Korea is ready to ramp up production.