VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP

Reducing the Resistance

GlobalFoundries spent most of their effort addressing the transistor resistance (RON).

Transistor diagram with the epi and contact shown (WikiChip)

From a cross-sectional view, the path of the RON is shown below. The three major components addressed were the channel resistance (Rchannel), the source-drain resistance (RSD), and the contact resistance (Rcontact).


Path of RON which includes the contact resistance, source-drain resistance, and the channel resistance (WikiChip)

Although they did not give an exact breakdown, a graph of the breakdown was shown at the presentation. We have reproduced the graph below and extrapolated the percent breakdown (might be slightly off). The channel resistance is around 54%, the contact resistance is around 25%, and the source-drain resistance in the epitaxy region is around 21%.

14LPP Resistance Breakdown (WikiChip)

Contact Resistance

To further enhance the contact resistance, GlobalFoundries optimized the contact profile by enlarging the bottom contact size, increasing the overall contact area. The doping profile directly under the tranch contact was also optimized in order to reduce the height of the contact barrier and reduce the contact resistance. The two optimizations were reported to provide around 12% reduction in contact resistance for nFET and around 35% reduction for pFET.

Contact Resistance improvements (VLSI 2018, GlobalFoundries)

Source-Drain Resistance

Cavity Depth (VLSI 2018, GlobalFoundries)
Addressing the resistance across the epitaxial source and drain regions is important for addressing the drive current and for the reduction of series resistance. The transistor performance is a direct function of the cavity depth. The bigger the depth, which results in a larger embedded SiGe area, increases the performance of the device but after a certain point, the higher leakage starts to negate most of the benefits. The improvement in performance becomes a very careful balancing act. GlobalFoundries optimized the pFET cavity depth at the optimal point of resistance/DIBL in order to extract around 4% higher performance at comparable leakage.

To further improve the pFET performance, GF modestly reduced the PLE (pattern loading effect) by optimizing the embedded silicon germanium cavity profile. The cavity in 12nm is now slightly deeper in order to allow for more eSiGe, improving channel strain. The 12nm 40-fin device showed around 4% improvement while the SDB devices showed around 5% improvement (2-fin devices saw no improvements).

pFET eSiGe Cavity (VLSI 2018, GlobalFoundries)

For the nFET transistors, the active phosphorus dopant density was increased through the optimization of the Si-P epitaxial process which is said to deliver around 6% nFET improvement in the Ron resistance over the comparable control conditions.

Channel Resistance

12LP Fin Profile Optimization (VLSI 2018, GlobalFoundries)
Scaling the channel length has resulted in the parasitic resistance and capacitance effects, negatively impacting the performance of the device. For their 12nm, GF optimized the profile of their fin in order to better control the short channel effects. The fins were made thinner and taller to provide higher drive current. Though no numbers were given, we estimate the fins to have a height in the low 40s nanometer. Improvement in the Fin surface roughness provided an improvement in carrier mobility. 6% and 9% carrier mobility improvements were reported for nFEt and pFET respectively.

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