Skip to content
Thursday, May 26, 2022
Latest:
  • Samsung 17nm follows Intel 16
  • Reincarnating The 6502 Using Flexible TFT Tech For IoT
  • Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC
  • Samsung-Esperanto Concept AI-SSD Prototype
  • EUV State, NXE:3600D, and Pellicle Readiness and Industrialization
WikiChip Fuse

WikiChip Fuse

Your Chips and Semi News

  • Home
  • Account
  • Main Site
  • Architectures
    • x86
    • ARM
    • RISC-V
    • Power ISA
    • MIPS
  • Supercomputers
  • 14 nm
  • 12nm
  • 10nm
  • 7nm
  • 5nm
Samsung 17nm follows Intel 16
Foundries Process Technologies Subscriber Only Content 

Samsung 17nm follows Intel 16

May 22, 2022May 22, 2022 David Schor
Reincarnating The 6502 Using Flexible TFT Tech For IoT
ISSCC 2022 Organic Electronics Processors 

Reincarnating The 6502 Using Flexible TFT Tech For IoT

May 8, 2022May 8, 2022 David Schor
Samsung 17nm follows Intel 16
Foundries Process Technologies Subscriber Only Content 

Samsung 17nm follows Intel 16

May 22, 2022May 22, 2022 David Schor
Reincarnating The 6502 Using Flexible TFT Tech For IoT
ISSCC 2022 Organic Electronics Processors 

Reincarnating The 6502 Using Flexible TFT Tech For IoT

May 8, 2022May 8, 2022 David Schor
Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC
Architectures Blockchain Processor ISSCC 2022 Processors 

Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC

February 20, 2022February 21, 2022 David Schor
Samsung-Esperanto Concept AI-SSD Prototype
Architectures Neural Processors 

Samsung-Esperanto Concept AI-SSD Prototype

November 21, 2021November 21, 2021 David Schor

Subscriber-Only ContentView All

Our latest subscriber-only content. Our patrons enjoy early-bird access to some of our content.

Samsung 17nm follows Intel 16
Foundries Process Technologies Subscriber Only Content 

Samsung 17nm follows Intel 16

May 22, 2022May 22, 2022 David Schor

Samsung follows Intel 16 with a low-cost high-performance, 17-nanometer, 17LPV node.

EUV State, NXE:3600D, and Pellicle Readiness and Industrialization
Foundries Process Technologies Roadmaps Subscriber Only Content 

EUV State, NXE:3600D, and Pellicle Readiness and Industrialization

November 20, 2021November 20, 2021 David Schor
Inside PFN’s AI Processor And The World’s Most Power-Efficient Supercomputer
Architectures Neural Processors Packaging Subscriber Only Content 

Inside PFN’s AI Processor And The World’s Most Power-Efficient Supercomputer

September 20, 2021September 20, 2021 David Schor
YouTube Accelerates Transcoding
Architectures Data Processing Unit Subscriber Only Content 

YouTube Accelerates Transcoding

August 21, 2021August 21, 2021 David Schor
Photonics Chiplet Inches Towards Production
Silicon Photonics Subscriber Only Content VLSI 2021 

Photonics Chiplet Inches Towards Production

August 16, 2021August 22, 2021 David Schor

ArchitecturesView All

Our latest coverage from the chip architecture world, including announced and planned as well as recently launched products.

Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC
Architectures Blockchain Processor ISSCC 2022 Processors 

Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC

February 20, 2022February 21, 2022 David Schor

Intel unveiled BonanzaMine, its first-generation blockchain accelerator ASIC effort.

Samsung-Esperanto Concept AI-SSD Prototype
Architectures Neural Processors 

Samsung-Esperanto Concept AI-SSD Prototype

November 21, 2021November 21, 2021 David Schor

Esperanto demonstrates a concept AI-SSD prototype in collaboration with Samsung aimed at accelerating data center workloads such as recommendation engines.

Intel Launches 12th Gen Core Desktop Alder Lake Processors
Architectures Desktop Processors 

Intel Launches 12th Gen Core Desktop Alder Lake Processors

October 27, 2021November 3, 2021 David Schor

Intel launches 12th Gen Core desktop processors based on the Alder Lake microarchitecture.

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor

Alibaba open-source its high-performance XuanTie RISC-V Cores; introduces a new in-house Armv9 server chip

Process TechnologyView All

Our latest coverage from the semiconductor world including recent announcements and analysis of new process nodes from semiconductor foundries including Intel, TSMC, Samsung, GlobalFoundries, and other.

Samsung 17nm follows Intel 16
Foundries Process Technologies Subscriber Only Content 

Samsung 17nm follows Intel 16

May 22, 2022May 22, 2022 David Schor

Samsung follows Intel 16 with a low-cost high-performance, 17-nanometer, 17LPV node.

EUV State, NXE:3600D, and Pellicle Readiness and Industrialization
Foundries Process Technologies Roadmaps Subscriber Only Content 

EUV State, NXE:3600D, and Pellicle Readiness and Industrialization

November 20, 2021November 20, 2021 David Schor
TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node
Foundries Process Technologies Roadmaps 

TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node

October 26, 2021October 26, 2021 David Schor
Intel 2021 Process Technology Update: Intel 7, Intel 4, Intel 3, and Intel 20A
Foundries Process Technologies Roadmaps 

Intel 2021 Process Technology Update: Intel 7, Intel 4, Intel 3, and Intel 20A

July 26, 2021July 26, 2021 David Schor
Intel Announces 20Å Node: RibbonFET Devices, PowerVia, 2024 Ramp
Foundries Process Technologies Roadmaps 

Intel Announces 20Å Node: RibbonFET Devices, PowerVia, 2024 Ramp

July 26, 2021July 26, 2021 David Schor

SupercomputersView All

The latest chip-related news from the world of HPC and supercomputers.

Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect
Architectures Hot Interconnects 26 Interconnects Supercomputers 

Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect

Japanese AI Startup Preferred Networks Designed A Custom Half-petaFLOPS Training Chip
Architectures Neural Processors Supercomputers Supercomputing 19 

Japanese AI Startup Preferred Networks Designed A Custom Half-petaFLOPS Training Chip

SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio
Architectures Roadmaps Server Processors Supercomputers Supercomputing 19 

SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio

Cavium Takes ARM to Petascale with Astra
Supercomputers 

Cavium Takes ARM to Petascale with Astra

Fujitsu Completes Post-K ARM CPU Prototype
Supercomputers 

Fujitsu Completes Post-K ARM CPU Prototype

ORNL’s 200-petaFLOPS Summit Supercomputer Has Arrived, To Become World’s Fastest
Supercomputers 

ORNL’s 200-petaFLOPS Summit Supercomputer Has Arrived, To Become World’s Fastest

A Look at Cavium’s New High-Performance ARM Microprocessors and the Isambard Supercomputer
Server Processors Supercomputers 

A Look at Cavium’s New High-Performance ARM Microprocessors and the Isambard Supercomputer

Japan cancels contract, kicks out 4th fastest supercomputer amid fraud charges
Supercomputers 

Japan cancels contract, kicks out 4th fastest supercomputer amid fraud charges

ConferencesView All

  • Reincarnating The 6502 Using Flexible TFT Tech For IoT
    ISSCC 2022 Organic Electronics Processors 

    Reincarnating The 6502 Using Flexible TFT Tech For IoT

  • Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC
    Architectures Blockchain Processor ISSCC 2022 Processors 

    Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC

  • A Look At Qualcomm’s Data Center Inference Accelerator
    Architectures Hot Chips 33 Linley Processor Conference Neural Processors 

    A Look At Qualcomm’s Data Center Inference Accelerator

  • Photonics Chiplet Inches Towards Production
    Silicon Photonics Subscriber Only Content VLSI 2021 

    Photonics Chiplet Inches Towards Production

  • Samsung 3nm GAA Inches Towards Productization With SRAM, SoC Test Vehicles
    Circuit Design Foundries ISSCC 2021 Process Technologies Roadmaps Subscriber Only Content VLSI 2021 

    Samsung 3nm GAA Inches Towards Productization With SRAM, SoC Test Vehicles

Reincarnating The 6502 Using Flexible TFT Tech For IoTReincarnating The 6502 Using Flexible TFT Tech For IoTIntel Unveils BonanzaMine, A Bitcoin Accelerator ASICIntel Unveils BonanzaMine, A Bitcoin Accelerator ASICA Look At Qualcomm’s Data Center Inference AcceleratorA Look At Qualcomm’s Data Center Inference AcceleratorPhotonics Chiplet Inches Towards ProductionPhotonics Chiplet Inches Towards ProductionSamsung 3nm GAA Inches Towards Productization With SRAM, SoC Test VehiclesSamsung 3nm GAA Inches Towards Productization With SRAM, SoC Test Vehicles

Top Six Articles

  • TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node
  • Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
  • The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids
  • TSMC 2021 Foundry Update: Foundry Roadmap
  • Intel Announces 20Å Node: RibbonFET Devices, PowerVia, 2024 Ramp
  • AMD 3D Stacks SRAM Bumplessly

Recent

  • Samsung 17nm follows Intel 16

    Samsung 17nm follows Intel 16

    May 22, 2022May 22, 2022 David Schor
  • Reincarnating The 6502 Using Flexible TFT Tech For IoT

    Reincarnating The 6502 Using Flexible TFT Tech For IoT

    May 8, 2022May 8, 2022 David Schor
  • Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC

    Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC

    February 20, 2022February 21, 2022 David Schor
  • Samsung-Esperanto Concept AI-SSD Prototype

    Samsung-Esperanto Concept AI-SSD Prototype

    November 21, 2021November 21, 2021 David Schor
  • EUV State, NXE:3600D, and Pellicle Readiness and Industrialization

    EUV State, NXE:3600D, and Pellicle Readiness and Industrialization

    November 20, 2021November 20, 2021 David Schor
  • Intel Launches 12th Gen Core Desktop Alder Lake Processors

    Intel Launches 12th Gen Core Desktop Alder Lake Processors

    October 27, 2021November 3, 2021 David Schor

Random Picks

Arm Launches Its New Flagship Performance Armv9 Core: Cortex-X2

Arm Launches Its New Flagship Performance Armv9 Core: Cortex-X2

May 25, 2021May 25, 2021 David Schor
Mythic Rolls Out M1000-Series Analog AI Accelerators; Raises $70M Along The Way

Mythic Rolls Out M1000-Series Analog AI Accelerators; Raises $70M Along The Way

August 22, 2021August 22, 2021 David Schor
Intel Axes Nervana Just Two Months After Launch

Intel Axes Nervana Just Two Months After Launch

February 3, 2020May 25, 2021 David Schor
Arm Launches the Cortex-M55 and Its MicroNPU Companion, the Ethos-U55

Arm Launches the Cortex-M55 and Its MicroNPU Companion, the Ethos-U55

February 10, 2020May 25, 2021 David Schor
Samsung Ramps 7nm, Preps 5nm, And Adds 6nm

Samsung Ramps 7nm, Preps 5nm, And Adds 6nm

April 16, 2019May 25, 2021 David Schor

Random Tags

2.5D packaging 3D packaging 5 nm 5nm 7 nm 7nm 10 nm 10nm 12nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 edge computing EMIB EUV FinFET Foveros GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

Intel Reveals Initial 9000-Series Coffee Lake SKUs

Intel Reveals Initial 9000-Series Coffee Lake SKUs

July 3, 2018May 25, 2021 David Schor
Intel Rolls Out Cascade Lake Xeon W Processors

Intel Rolls Out Cascade Lake Xeon W Processors

June 3, 2019May 25, 2021 David Schor
7nm Boosted Zen 2 Capabilities but Doubled the Challenges

7nm Boosted Zen 2 Capabilities but Doubled the Challenges

February 21, 2020May 25, 2021 David Schor
Intel discloses Tremont, a Goldmont Plus successor

Intel discloses Tremont, a Goldmont Plus successor

April 4, 2018May 25, 2021 David Schor
A Look At The Habana Inference And Training Neural Processors

A Look At The Habana Inference And Training Neural Processors

December 15, 2019May 25, 2021 David Schor
AMD’s New EPYC 7H12: A Specially-Binned HPC Processor

AMD’s New EPYC 7H12: A Specially-Binned HPC Processor

September 20, 2019May 25, 2021 David Schor
Nvidia Inference Research Chip Scales to Dozens of Chiplets

Nvidia Inference Research Chip Scales to Dozens of Chiplets

June 30, 2019May 25, 2021 David Schor

ARM WorldView All

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor
A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip
IEDM 2020 Interconnects Packaging Subscriber Only Content 

A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

June 11, 2021June 11, 2021 David Schor
Arm Launches New Coherent And SoC Interconnects: CI-700 & NI-700
Architectures Interconnects Network-on-Chip 

Arm Launches New Coherent And SoC Interconnects: CI-700 & NI-700

May 25, 2021May 25, 2021 David Schor
Arm Launches The DSU-110 For New Armv9 CPU Clusters
Architectures Interconnects Mobile Processors 

Arm Launches The DSU-110 For New Armv9 CPU Clusters

May 25, 2021May 25, 2021 David Schor

About

WikiChip
WikiChip is an independent publisher based in New York. The WikiChip Fuse section publishes chips and semiconductor related news with our main site offering in-depth semiconductor resources and analysis.

WikiChip Links

  • Main Site
  • WikiChip Fuse
  • Newsletter
  • Main Site
  • WikiChip Fuse

Copyright © 2022 WikiChip LLC. All rights reserved.