VLSI 2018: Samsung’s 2nd Gen 7nm, EUV Goes HVM

SRAM

EUV superior patterning and simplified routing allowed them to design highly competitive memory. Samsung claims that compared to multi-patterning ArF based design, single-patterning 2D EUV results in up to 50% smaller layout pattern.

This that end, Samsung is reporting the highest-density SRAM bit-cell size of 0.0262 µm².

Special Constructs

Just like Intel’s 10nm and their “hyper-scaling” techniques, Samsung introduced a couple of special constructs in order to improve the density of their process.

Height Reduction

Samsung developed a special construct which leverages EUV in order to reduce the cell height.

This special construct provides similar scaling benefits to Intel’s COAG booster, albeit they are fundamentally very different technologies. Both techniques push density for another ~10% area scaling. Note that this special construct is only possible for this node with the help of EUV.

Single Dummy Gate

Introduced in their 14nm process, Samsung did not initially use it for their 1st generation 7nm. However, with their second generation, Samsung re-introduced SDB. The single-diffusion break contributes around 15-20% additional density improvement.

One thing they improved this time around is better stability across various layouts through better suppression of local layout effects.

Leading Density

With a cell height of 9 fin pitches (243 nm) and taking into account the use of a single dummy gate, using Intel’s MTr/mm² weighted density metric, Samsung’s 2nd generation 7nm HD cell yields 112.79 MTr/mm². We were also told that Samsung is not using the reported 54nm poly pitch for their standard cell but a slightly more relaxed pitch of 57-58nm. It seems that the 57nm pitch is also mentioned elsewhere on the internet. Even with a 57nm poly pitch, this process node provides a density of 106.85 MTr/mm². Both values are the highest densities of any leading-edge process presented to date.