Architectures

Intel’s Diamond Mesa Bridges The Gap Between ASIC and FPGA

June 13, 2021June 13, 2021 David Schor 16 nm, Diamond Mesa, eASIC Nextreme, Intel, Intel eASIC, Structured ASIC, subscriber only (general)

With Intel’s acquisition of eASIC in 2018, the company’s latest product – codenamed Diamond Mesa – attempts to bridge the gap between full ASIC and FPGAs.

Architectures Desktop Processors Interconnects Packaging

AMD 3D Stacks SRAM Bumplessly

June 7, 2021June 7, 2021 David Schor 3D packaging, 3D V-Cache, 7 nm, AMD, Direct Bond Interconnect (DBI), hybrid bonding, Ryzen, SRAM, System on Integrated Chips (SoIC)

AMD recently unveiled 3D V-Cache, their first 3D-stacked technology-based product. Leapfrogging contemporary 3D bonding technologies, AMD jumped directly into advanced packaging with direct bonding and an order of magnitude higher wire density.

Architectures Interconnects Network-on-Chip

Arm Launches New Coherent And SoC Interconnects: CI-700 & NI-700

May 25, 2021May 25, 2021 David Schor ARM, ARMv9, cache coherency, CI-700, CMN-700, CoreLink, interconnects, Memory Tagging Extension (MTE), mesh interconnect, NI-700

Arm is introducing a new cache-coherent and SoC-level interconnects, the CoreLink CI-700 & NI-700.

Architectures Interconnects Mobile Processors

Arm Launches The DSU-110 For New Armv9 CPU Clusters

May 25, 2021May 25, 2021 David Schor ARM, ARMv9, DSU-110, Memory Tagging Extension (MTE)

Arm introduces its new DynamIQ Share Unit 110 for new Armv9 CPUs

Architectures Embedded Processors Mobile Processors

Arm Launches Its New Flagship Performance Armv9 Core: Cortex-X2

May 25, 2021May 25, 2021 David Schor ARM, ARMv9, Cortex-X, Cortex-X2, Scalable Vector Extension 2 (SVE2)

Arm launches the Cortex-X2, second-generation Cortex-X, and their new flagship performance Armv9 big core.

Architectures Embedded Processors Mobile Processors

Arm Unveils Next-Gen Armv9 Little Core: Cortex-A510

May 25, 2021May 26, 2021 David Schor ARM, ARMv9, Cortex-A, Cortex-A510, Scalable Vector Extension 2 (SVE2)

Arm introduces their new Armv9 little core, the Cortex-A510 with significant PPA improvements.

Architectures Embedded Processors Mobile Processors

Arm Unveils Next-Gen Armv9 Big Core: Cortex-A710

May 25, 2021May 25, 2021 David Schor ARM, ARMv9, Cortex-A, Cortex-A710, Scalable Vector Extension 2 (SVE2)

Arm unveils their newest Armv9 big core, the Cortex-A710.

Architectures Interconnects

The Mesh Network For Next-Generation Neoverse Chips

May 22, 2021May 23, 2021 David Schor ARM, CMN-600, CMN-700, DDR5, mesh interconnect, neoverse, Neoverse N, Neoverse V, PCIe 5.0

Arm’s CMN-700 is the company’s latest high-performance cache-coherent mesh interconnect for the server market, enabling SoC designs with twice as many cores, as much as half a GiB of cache, dozens of memory controllers, and support dozens of cache-coherent accelerators, chiplets, and processors.

Architectures Graphics Processors Hot Chips 33 Mobile Processors Neural Processors Server Processors Vector Processors

Hot Chips 33 Program: Alder Lake, Sapphire Rapids, Zen 3, Next-Gen Z, Neoverse N2, And Many More

May 13, 2021May 23, 2021 David Schor AMD, ARM, Cerebras, Esperanto, Hot Chips, Hot Chips 33, Intel, Nvidia

The IEEE Symposium on High-Performance Chips Program Committee announced the program for the 2021 Hot Chips 33 conference.

Architectures Server Processors

Arm Launches New Neoverse N2 and V1 Server CPUs: 1.4x-1.5x IPC, SVE, and ARMv9

April 27, 2021May 23, 2021 David Schor ARM, ARMv9, bfloat16, Neoverse N, Neoverse V, Perseus, Scalable Vector Extension (SVE), Scalable Vector Extension 2 (SVE2), Zeus

Arm launches its next-generation server CPUs – Neoverse N2 and Neoverse V1 (formerly Perseus and Zeus). Targeting high-performance servers and the HPC market, the new cores bring 1.4-1.5x higher IPC , SVE support, BFloat16, and the ARMv9 architecture.