A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC
A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered accelerator.
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DARPA
DARPA ERI: HIVE and Intel PUMA Graph Processor
An update on the DAPRA HIVE program and the first disclosure of Intel’s Graph Analytics (GA) processor that is currently under development
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DARPA ERI: How Ayar Labs Collaboration With GF Produces A Photonics Chiplet That Can Supercharge Intel FPGAs
From a DARPA vision and a $15 million seed to a commercialized CMOS silicon photonics product: how Ayar Labs collaboration with GF produces a photonics chiplet that can supercharge Intel FPGAs.
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Intel Labs Builds A Neuromorphic System With 64 To 768 Loihi Chips: 8 Million To 100 Million Neurons
Intel announced Pohoiki Beach and Pohoiki Springs, two new research neuromorphic systems capable of scaling from 64 to 768 Loihi chips with 8 million to 100 million neurons per system.
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Intel Opens AIB for DARPA’s CHIPS Program as a Royalty-Free Interconnect Standard for Chiplet Architectures
At the DARPA 2018 ERI Summit, Intel announced their contribution of a royalty-free bus standard to DARPA’s CHIPS Program, allowing seamless communication between multiple packaged chiplets.
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