A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip
A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI cores using 1.2 trillion transistors on a half square foot of silicon.
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Architectures
Groq Tensor Streaming Processor Delivers 1 PetaOPS of Compute
AI startup Groq makes an initial disclosure of their Tensor Streaming Processor (TSP); a single chip capable of 1 petaOPS or 250 teraFLOPS of compute.
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A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor
A look at the microarchitecture of Intel Nervana next-generation data center training neural processor, codename Spring Crest.
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IBM Adds POWER9 AIO, Pushes for an Open Memory-Agnostic Interface
IBM adds a third variant of POWER9, the POWER9 Advanced I/O (AIO) processor which incorporates the Open Memory Interface (OMI), a new open memory-agnostic interface.
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Intel Unveils the Tremont Microarchitecture: Going After ST Performance
Intel unveils the Tremont microarchitecture, its next-generation low-power small x86 core.
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Intel Spring Hill: Morphing Ice Lake SoC Into A Power-Efficient Data Center Inference Accelerator
First detailed at Hot Chips 31, Intel Spring Hill morphs the Ice Lake SoC into a highly power-efficient data center inference accelerator.
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Analog AI Startup Mythic To Compute And Scale In Flash
A look at the IPU architecture of analog AI startup Mythic which attempts to significantly reduce the power consumption by computing directly in analog in flash.
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Alibaba Launches DC Inference Accelerators
Alibaba launches its own homegrown inference accelerator for their own cloud.
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Inside Tesla’s Neural Processor In The FSD Chip
A deep dive into the custom-designed Tesla neural processing units integrated inside the company’s full self-driving (FSD) chip based on the Tesla Hot Chips 31 talk.
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GlobalFoundries, Arm Demonstrate High-Density 3D Stacked Mesh Interconnect for HPC Applications
GlobalFoundries and Arm demonstrate a 3D mesh interconnect design using highly-dense hybrid bonding 3D stacking technology intended for HPC applications.
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