A Look At Samsung’s 4LPE Process
A look at Samsung’s last leading-edge FinFET process node, 4nm 4LPE.
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FinFET
TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node
TSMC introduces a new 5-nanometer derivative – an enhanced performance N4P node.
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TSMC 2021 Foundry Update: Foundry Roadmap
TSMC 2021 foundry update
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Q1 2021 Foundry Update: Spending Bonanza
A look at the current state of leading-edge foundries for the first quarter of 2021.
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TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter
TSMC reports a flat Q1 amid the COVID-19 pandemic, ramps its 5nm node with good yield and discloses key 3-nanometer (N3) details. N3 will be a full node jump over N5 and is expected to offer over a quarter-billion transistors per each millimeter square of silicon.
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TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO
Update and analysis of TSMC 7-nanometer node low-power and high-performance cells, 2nd generation 7nm, and the design technology co-optimization (DTCO) effort that went into the Snapdragon 855 SoC.
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TSMC Starts 5-Nanometer Risk Production
TSMC 5-nanometer node has entered risk production with PDKs available for production design. Here’s is our initial density estimates.
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VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP
A look at GlobalFoundries 12nm Leading Performance technology, 12LP, an enhanced 14nm process. The process was recently presented at the 2018 Symposia on VLSI Technology and Circuits.
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VLSI 2018: Samsung’s 8nm 8LPP, a 10nm extension
A look at Samsung’s 8nm 8LPP process that was recently disclosed at the 38th Symposium on VLSI Technology.
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VLSI 2018: Samsung’s 11nm nodelet, 11LPP
A look at Samsung’s 11nm 11LPP process that was recently disclosed at the 38th Symposium on VLSI Technology.
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