WikiChip Fuse
A look at Nvidia’s NVLink interconnect and the NVSwitch

A look at Nvidia’s NVLink interconnect and the 2-billion transistor NVSwitch that is powering Nvidia’s latest DGX-2 deep learning machine.

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QUEST, A TCI-Based 3D-Stacked SRAM Neural Processor

Attempting to address the memory bandwidth problem, the QUEST neural processor uses 3D-stacked SRAM dies along with ThruChip Interface wireless communication technology to deliver sufficiently high bandwidth to sustain peak processing performance.

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AMD’s Zen CPU Complex, Cache, and SMU

A look at AMD’s Zen CPU Complex (CCX), a fully independent and modular cluster of up to four cores that are incorporated into a full SoC to form complete products such as their Zeppelin die.

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Intel discloses Tremont, a Goldmont Plus successor

Intel has disclosed a new “Tremont” microarchitecture along with the release of their latest architecture ISA programming reference.

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ISSCC 2018: Intel’s Self-Powered Intelligent IoT Edge Mote

A look at Intel’s tiny intelligent IoT edge mote operating at near-threshold voltage and harvesting solar energy for charging. Equipped with sensors and an SoC with hardware to accelerate convolutional neural networks (CNNs), the chip collects environmental sensory data and captures images which are classified on-chip and sent to a data center in order to improve and optimize agricultural fields.

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ISSCC 2018: AMD’s Zeppelin; Multi-chip routing and packaging

A look at AMD’s Zeppelin SoC and the Infinity Fabric, a multi-chip architecture used by AMD to scale their SoC design from the mainstream PC market all the way to the server market.

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ISSCC 2018: MIT’s low-power hardware crypto RISC-V IoT processor

In recent years, IoT devices have been plagued with security issues. Memory and energy constraints of those low-power devices mean there is very little headroom for complex security implementations. At ISSCC 2018, a team of MIT researchers has attempted to address this problem with their low-power fully in-hardware crypto engine IoT RISC-V processor.

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ISSCC 2018: Intel’s Skylake-SP Mesh and  Floorplan

At ISSCC 2018 Intel gave us some more interesting architectural details of their latest Skylake server microprocessors which brought a new mesh interconnect, a new cache hierarchy, and wider vector operations among a large array of other enhancements.

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Goldmont Plus detailed, large improvements, setting the stage for a 32-core model

Intel has finally detailed their recently launched Goldmont Plus microarchitecture and unlike what the name suggests, this is very far from a simple refresh.

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Intel’s Total Memory Encryption, a new x86 extension for full memory encryption

Intel has released the first revision of their new x86 specification that adds support for page-granular and full physical memory encryptions.

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