WikiChip Fuse
ISSCC 2018: MIT’s low-power hardware crypto RISC-V IoT processor

In recent years, IoT devices have been plagued with security issues. Memory and energy constraints of those low-power devices mean there is very little headroom for complex security implementations. At ISSCC 2018, a team of MIT researchers has attempted to address this problem with their low-power fully in-hardware crypto engine IoT RISC-V processor.

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ISSCC 2018: Intel’s Skylake-SP Mesh and  Floorplan

At ISSCC 2018 Intel gave us some more interesting architectural details of their latest Skylake server microprocessors which brought a new mesh interconnect, a new cache hierarchy, and wider vector operations among a large array of other enhancements.

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Goldmont Plus detailed, large improvements, setting the stage for a 32-core model

Intel has finally detailed their recently launched Goldmont Plus microarchitecture and unlike what the name suggests, this is very far from a simple refresh.

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Intel’s Total Memory Encryption, a new x86 extension for full memory encryption

Intel has released the first revision of their new x86 specification that adds support for page-granular and full physical memory encryptions.

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