A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC
A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered accelerator.
Read moreA look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered accelerator.
Read moreA look at the Habana inference and training neural processors designed for the acceleration of data center workloads.
Read moreCentaur lifts the veil on CNS, its next-generation x86 core for data center and edge computing. The core improving performance in many areas and adds support for the AVX-512 extension.
Read moreIntel starts shipping its initial Nervana NNP lineup for both inference and training acceleration with four initial models in three different form factors.
Read moreJapanese AI Startup Preferred Networks has been working on a custom training chip with a peak performance of half-petaFLOPS as well as a supercomputer with a peak performance of 2 exaFLOPS (HP).
Read moreA look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI cores using 1.2 trillion transistors on a half square foot of silicon.
Read moreAI startup Groq makes an initial disclosure of their Tensor Streaming Processor (TSP); a single chip capable of 1 petaOPS or 250 teraFLOPS of compute.
Read moreIntel announces Keem Bay, its 3rd-generation Movidius VPU edge inference processor.
Read moreA look at the microarchitecture of Intel Nervana next-generation data center training neural processor, codename Spring Crest.
Read moreFirst detailed at Hot Chips 31, Intel Spring Hill morphs the Ice Lake SoC into a highly power-efficient data center inference accelerator.
Read more