WikiChip Fuse
IBM Releases Power ISA v3.1; To Present POWER10 At Hot Chips 32

IBM releases Power ISA v3.1. Among the new instructions, there is new bfloat16 support, new reduced-precision outer-product operations including 4-bit integers, and new instruction prefixes. IBM plans on presenting POWER10 at Hot Chips 32.

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A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC

A look at Lakefield, Intel’s new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company Foveros packaging technology.

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Ayar Labs Realizes Co-Packaged Silicon Photonics

Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step forward through the co-packaging of the optical interface along with an SoC.

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A Look At The Habana Inference And Training Neural Processors

A look at the Habana inference and training neural processors designed for the acceleration of data center workloads.

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A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip

A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI cores using 1.2 trillion transistors on a half square foot of silicon.

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A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor

A look at the microarchitecture of Intel Nervana next-generation data center training neural processor, codename Spring Crest.

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IBM Adds POWER9 AIO, Pushes for an Open Memory-Agnostic Interface

IBM adds a third variant of POWER9, the POWER9 Advanced I/O (AIO) processor which incorporates the Open Memory Interface (OMI), a new open memory-agnostic interface.

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Intel Spring Hill: Morphing Ice Lake SoC Into A Power-Efficient Data Center Inference Accelerator

First detailed at Hot Chips 31, Intel Spring Hill morphs the Ice Lake SoC into a highly power-efficient data center inference accelerator.

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Inside Tesla’s Neural Processor In The FSD Chip

A deep dive into the custom-designed Tesla neural processing units integrated inside the company’s full self-driving (FSD) chip based on the Tesla Hot Chips 31 talk.

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A Look at NEC’s Latest Vector Processor, the SX-Aurora

A look at the NEC SX-Aurora, their latest vector processor – increasing compute while maintaining a high B/F through six HBM2 modules leveraging TSMC 2nd gen CoWoS technology. The SX-Aurora introduces a new form factor, system architecture, and execution model.

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