7nm Boosted Zen 2 Capabilities but Doubled the Challenges
The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.
Read moreThe transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.
Read moreA dive into the Rosetta ASIC switch, the engine behind Cray’s new Slingshot interconnect powering the upcoming Shasta exascale supercomputers.
Read moreArm’s Ethos family takes aim at ubiquitous AI with NPUs for ultra-low power IoT to high-performance smartphones and AR/VR.
Read moreIntegrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step forward through the co-packaging of the optical interface along with an SoC.
Read moreA look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered accelerator.
Read moreAMD launches new value and entry-level mobile processors, codenamed Dali.
Read moreA look at a Bunch of Wires, a new open standard chiplets interconnect being proposed by the OCP ODSA group intended for standard organic multi-chip packages as a cheaper alternative to silicon interposers and bridges.
Read moreA look at the Habana inference and training neural processors designed for the acceleration of data center workloads.
Read moreTSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.
Read moreIntel’s process technology roadmap reveals decade-out plans, including a future 10nm+++ node and even a 1.4nm node heading into 2029.
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