A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC
A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered accelerator.
Read moreA look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered accelerator.
Read moreIntel expands its 22FFL process with new production-ready MRAM and RRAM technologies.
Read moreAn update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.
Read moreNvidia recently presented a research chip comprising dozens of chiplets that enables them to scale from milliwatts to hundreds of watts in order to cater to different markets such as edge, mobile, automotive, and data center.
Read moreA look at a high-performance 7nm Arm-based chiplet architecture which was recently presented by TSMC at the 2019 VLSI Symposium.
Read moreUpdate and analysis of TSMC 7-nanometer node low-power and high-performance cells, 2nd generation 7nm, and the design technology co-optimization (DTCO) effort that went into the Snapdragon 855 SoC.
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