A Look At The Ice Lake Thunderbolt 3 Integration
At look the Ice Lake Thunderbolt 3 integration, Intel’s biggest integration since the graphics on Sandy Bridge.
Read more
Interconnects
Intel Introduces Co-EMIB To Stitch Multiple 3D Die Stacks Together, Adds Omni-Directional Interconnects
Intel is expanding its packaging portfolio with more advanced 2.5D and 3D technologies including multiple 3D stacks and omnidirectional interconnects.
Read more
Nvidia Inference Research Chip Scales to Dozens of Chiplets
Nvidia recently presented a research chip comprising dozens of chiplets that enables them to scale from milliwatts to hundreds of watts in order to cater to different markets such as edge, mobile, automotive, and data center.
Read more
TSMC Demonstrates A 7nm Arm-Based Chiplet Design for HPC
A look at a high-performance 7nm Arm-based chiplet architecture which was recently presented by TSMC at the 2019 VLSI Symposium.
Read more
Intel Process Technology And Packaging Plans: 10nm in June, 7nm in 2021
An outline of Intel’s process technology and packaging plans including their 10nm and 7nm nodes as discussed at the company’s recent investor meeting.
Read more
Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes
At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.
Read more
POWER9 Scales Up To 1.2 TB/s of I/O, Targets NVLink 3, OpenCAPI Memory for 2019
A look at the IBM POWER9 scale-up design recently disclosed at Hot Chips 30 and their plans for a 3rd POWER9 derivative for 2019.
Read more
Nantero’s NRAM, A Universal Memory Candidate?
Presented at Hot Chips 30, a look at Nantero’s NRAM, a high-performance carbon nanotube-based memory billed as a DRAM successor.
Read more
Intel Opens AIB for DARPA’s CHIPS Program as a Royalty-Free Interconnect Standard for Chiplet Architectures
At the DARPA 2018 ERI Summit, Intel announced their contribution of a royalty-free bus standard to DARPA’s CHIPS Program, allowing seamless communication between multiple packaged chiplets.
Read more