TSMC Demos SoIC_H for High-Bandwidth HPC Applications
[Subscription] TSMC demonstrates SoIC_H for next-generation high-bandwidth HPC applications.
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2.5D packaging
5th Gen CoWoS-S Extends 3 Reticle Size
TSMC’s 5th Generation CoWoS-S Extends 3 Reticle Size.
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Inside Baidu’s In-House Neural Processor
A peek inside Baidu’s in-house neural processor
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Left, Right, Above, and Under: Intel 3D Packaging Tech Gains Omnidirectionality
A look at ODI, a new family of packaging interconnect technologies that bridges the gap between Intel’s EMIB (2.5D) and Foveros (3D) by providing the flexibility of an EMIB in 3D with additional benefits of thermal & power.
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TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications
TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The new technology is ready for next-generation 5-nanometer HPC applications.
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OCP Makes a Push for an Open Chiplet Marketplace
Jumping ahead of emerging semiconductor trends, the OCP new Open Domain-Specific Architecture subgroup makes a push for an open and standardized chiplet interface and marketplace.
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TSMC Digs Trenches In Search Of Higher Performance
TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.
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Intel Launches Stratix 10 GX 10M; 10M LEs, Two Massive Interconnected Dies
Intel launches the industry’s highest-capacity FPGA; 10-million LEs comprising two large FPGA dies interconnected using the company’s 2.5D EMIB packaging technology.
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Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes
At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.
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Samsung 7nm Enters Risk Production, Talks Roadmap, Scaling Boosters, and the ARM Ecosystem
Samsung gives an update on their 7nm EUV-based process, details the foundry technology roadmap down to 3nm and the ARM ecosystem that follows.
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