Samsung 3nm GAA Inches Towards Productization With SRAM, SoC Test Vehicles
Samsung tapes out 3nm GAA test vehicle as it inches towards mass production
Read moreSamsung tapes out 3nm GAA test vehicle as it inches towards mass production
Read moreA TSMC 2021 foundry update: automotive, networking, and HPC roadmap.
Read moreTSMC 2021 foundry update
Read moreIntel talks 10-nanometers DTCO and the benefits of EUV on their future 7 nm and 5 nm nodes.
Read moreSamsung revealed more details of its 5LPE process technology which recently ramped, gave a roadmap status update along with new stop-gap nodes announcement.
Read moreA look at ODI, a new family of packaging interconnect technologies that bridges the gap between Intel’s EMIB (2.5D) and Foveros (3D) by providing the flexibility of an EMIB in 3D with additional benefits of thermal & power.
Read moreTSMC reports a flat Q1 amid the COVID-19 pandemic, ramps its 5nm node with good yield and discloses key 3-nanometer (N3) details. N3 will be a full node jump over N5 and is expected to offer over a quarter-billion transistors per each millimeter square of silicon.
Read moreTSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry’s highest density transistors with a high-mobility channel and highest-density SRAM cells.
Read moreTSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The new technology is ready for next-generation 5-nanometer HPC applications.
Read moreTSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.
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