Process Technologies

UMC Rolls Out 22-Nanometer

December 13, 2019May 25, 2021 David Schor 22 nm, 22ULL, 22ULP, 28nm, 40 nm, UMC

UMC says it has started rolling out its 22-nanometer planar process, offering a new lower-power and cost-sensitive migration path from existing 40nm and 28nm nodes.

IEDM 2019 Process Technologies Roadmaps

Intel 2020s Process Technology Roadmap: 10nm+++, 3nm, 2nm, and 1.4nm for 2029

December 10, 2019May 25, 2021 David Schor 1.4 nm, 10 nm, 10nm, 2 nm, 3 nm, 5 nm, 7 nm, Intel

Intel’s process technology roadmap reveals decade-out plans, including a future 10nm+++ node and even a 1.4nm node heading into 2029.

ARM TechCon 2019 Foundries Process Technologies

TSMC 5-Nanometer Update

November 1, 2019May 25, 2021 David Schor 5nm, 6nm, 7nm, EUV, N5, N6, N7, TSMC

An update on TSMC’s upcoming 5-nanometer process technology.

ARM TechCon 2019 Process Technologies Roadmaps

Samsung 5 nm and 4 nm Update

October 19, 2019May 25, 2021 David Schor 4LPE, 4nm, 5LPE, 5nm, Samsung

Update and analysis of Samsung’s upcoming 5-nanometer and 4-nanometer process technologies.

Process Technologies VLSI 2019

Intel Expands 22FFL With Production-Ready RRAM and MRAM on FinFET

October 18, 2019May 25, 2021 David Schor 22 nm, 22FFL, Intel, Intel Custom Foundry, MRAM, non-volatile memory, ReRAM, RRAM, VLSI 2019, VLSI Symposium

Intel expands its 22FFL process with new production-ready MRAM and RRAM technologies.

Process Technologies

TSMC N7+ EUV Process Starts Shipping

October 7, 2019May 25, 2021 David Schor 7nm, EUV, N6, N7, TSMC

TSMC announces its N7+ process which entered HVM earlier this year is now shipping products to market.

Architectures Interconnects Packaging Process Technologies

GlobalFoundries, Arm Demonstrate High-Density 3D Stacked Mesh Interconnect for HPC Applications

September 21, 2019June 11, 2021 David Schor 12LP, 12nm, 3D packaging, ARM, CMN-600, design-for-test, Direct Bond Interconnect (DBI), GlobalFoundries, hybrid bonding, Trishul (Arm test chip)

GlobalFoundries and Arm demonstrate a 3D mesh interconnect design using highly-dense hybrid bonding 3D stacking technology intended for HPC applications.

Packaging Process Technologies SEMICON West 2019 VLSI 2019

TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging

July 28, 2019May 25, 2021 David Schor 3D packaging, 3nm, 5nm, 6nm, 7nm, CoWoS, InFO, InFO_AiP, InFO_MS, InFO_oS, N5, N5P, N6, N7, N7P, SemiConWest, SoIC, TSMC, VLSI 2019, VLSI Symposium

An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.

Process Technologies VLSI 2019

TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO

June 16, 2019May 25, 2021 David Schor 7HPC, 7nm, FinFET, SDM845, SDM855, Snapdragon 800, Snapdragon 855, TSMC, VLSI 2019, VLSI Symposium

Update and analysis of TSMC 7-nanometer node low-power and high-performance cells, 2nd generation 7nm, and the design technology co-optimization (DTCO) effort that went into the Snapdragon 855 SoC.

Foundries Interconnects Packaging Process Technologies

Intel Process Technology And Packaging Plans: 10nm in June, 7nm in 2021

May 11, 2019May 25, 2021 David Schor 10nm, 3D packaging, 7nm, EMIB, HPC, Lakefield

An outline of Intel’s process technology and packaging plans including their 10nm and 7nm nodes as discussed at the company’s recent investor meeting.