Hot Chips 30: AMD Raven Ridge
Overview of AMD Raven Ridge APUs that were recently detailed at Hot Chips 30.
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Circuit Design
A Look at Intel’s 10nm Std Cell as TechInsights Reports on the i3-8121U, finds Ruthenium
WikiChip takes another look at Intel’s 10-nanometer standard cell design and discusses TechInsights findings of the first 10nm-based chip, the i3-8121U.
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ISSCC 2018: The IBM z14 Microprocessor And System Control Design
A look at the changes and enhancements that were implemented by IBM in their z14 mainframe microprocessor and system control chips.
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A look at Nvidia’s NVLink interconnect and the NVSwitch
A look at Nvidia’s NVLink interconnect and the 2-billion transistor NVSwitch that is powering Nvidia’s latest DGX-2 deep learning machine.
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QUEST, A TCI-Based 3D-Stacked SRAM Neural Processor
Attempting to address the memory bandwidth problem, the QUEST neural processor uses 3D-stacked SRAM dies along with ThruChip Interface wireless communication technology to deliver sufficiently high bandwidth to sustain peak processing performance.
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AMD’s Zen CPU Complex, Cache, and SMU
A look at AMD’s Zen CPU Complex (CCX), a fully independent and modular cluster of up to four cores that are incorporated into a full SoC to form complete products such as their Zeppelin die.
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ISSCC 2018: AMD’s Zeppelin; Multi-chip routing and packaging
A look at AMD’s Zeppelin SoC and the Infinity Fabric, a multi-chip architecture used by AMD to scale their SoC design from the mainstream PC market all the way to the server market.
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ISSCC 2018: MIT’s low-power hardware crypto RISC-V IoT processor
In recent years, IoT devices have been plagued with security issues. Memory and energy constraints of those low-power devices mean there is very little headroom for complex security implementations. At ISSCC 2018, a team of MIT researchers has attempted to address this problem with their low-power fully in-hardware crypto engine IoT RISC-V processor.
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ISSCC 2018: Intel’s Skylake-SP Mesh and Floorplan
At ISSCC 2018 Intel gave us some more interesting architectural details of their latest Skylake server microprocessors which brought a new mesh interconnect, a new cache hierarchy, and wider vector operations among a large array of other enhancements.
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