ISSCC

TSMC Details 5 nm

Foundries IEDM 2019 ISSCC 2020 Process Technologies March 21, 2020 0

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry’s highest density transistors with a high-mobility channel and highest-density SRAM cells.

IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache

Architectures Circuit Design ISSCC 2020 March 8, 2020 5

IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of cache on the latest z15 microprocessor and system controller.

CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

Architectures Circuit Design ISSCC 2020 Manycore Processors Server Processors March 1, 2020 0

CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active interposer die.

Radeon RX 5700: Navi and the RDNA Architecture

Architectures Circuit Design Graphics Processors ISSCC 2020 February 23, 2020 1

A look at AMD’s Radeon RX 5700 GPU built on a 7-nanometer process based on the new Navi microarchitecture and RDNA graphics architecture.

7nm Boosted Zen 2 Capabilities but Doubled the Challenges

Architectures Floorplanning Interconnects ISSCC 2020 February 21, 2020 2

The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.

ISSCC 2018: The IBM z14 Microprocessor And System Control Design

Architectures Circuit Design Floorplanning ISSCC 2018 Server Processors May 13, 2018 4

A look at the changes and enhancements that were implemented by IBM in their z14 mainframe microprocessor and system control chips.

QUEST, A TCI-Based 3D-Stacked SRAM Neural Processor

Architectures Circuit Design ISSCC 2018 Neural Processors April 25, 2018 0

Attempting to address the memory bandwidth problem, the QUEST neural processor uses 3D-stacked SRAM dies along with ThruChip Interface wireless communication technology to deliver sufficiently high bandwidth to sustain peak processing performance.

AMD’s Zen CPU Complex, Cache, and SMU

Architectures Circuit Design ISSCC 2018 April 18, 2018 0

A look at AMD’s Zen CPU Complex (CCX), a fully independent and modular cluster of up to four cores that are incorporated into a full SoC to form complete products such as their Zeppelin die.

ISSCC 2018: Intel’s Self-Powered Intelligent IoT Edge Mote

Architectures Embedded Processors ISSCC 2018 April 2, 2018 0

A look at Intel’s tiny intelligent IoT edge mote operating at near-threshold voltage and harvesting solar energy for charging. Equipped with sensors and an SoC with hardware to accelerate convolutional neural networks (CNNs), the chip collects environmental sensory data and captures images which are classified on-chip and sent to a data center in order to improve and optimize agricultural fields.

ISSCC 2018: AMD’s Zeppelin; Multi-chip routing and packaging

Architectures Circuit Design Floorplanning ISSCC 2018 March 24, 2018 6

A look at AMD’s Zeppelin SoC and the Infinity Fabric, a multi-chip architecture used by AMD to scale their SoC design from the mainstream PC market all the way to the server market.