ISSCC

Reincarnating The 6502 Using Flexible TFT Tech For IoT

May 8, 2022May 8, 2022 David Schor 6502, Indium Gallium Zinc Oxide (IGZO), ISSCC, ISSCC 2022, MOS Technology 6502, Organic Electronics, Thin-film Transistor (TFT)

Can the 1970s MOS Technology 6502 find new life and new applications in the emerging world of plastic electronics?

Architectures Blockchain Processor ISSCC 2022 Processors

Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC

February 20, 2022February 21, 2022 David Schor 7 nm, ASIC, Bitcoin, blockchain accelerator, BonanzaMine, cryptocurrency, cryptocurrency mining, Intel, ISSCC, ISSCC 2022

Intel unveiled BonanzaMine, its first-generation blockchain accelerator ASIC effort.

Circuit Design Foundries ISSCC 2021 Process Technologies Roadmaps Subscriber Only Content VLSI 2021

Samsung 3nm GAA Inches Towards Productization With SRAM, SoC Test Vehicles

July 8, 2021July 8, 2021 David Schor 3 nm, GAA, Samsung, Samsung Foundry, subscriber only (general)

Samsung tapes out 3nm GAA test vehicle as it inches towards mass production

Architectures Hot Chips 31 IEDM 2019 ISSCC 2020

A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC

April 5, 2020May 25, 2021 David Schor 10 nm, 22 nm, 22FFL, 3D packaging, Foveros, Intel, Lakefield, Sunny Cove, Tremont

A look at Lakefield, Intel’s new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company Foveros packaging technology.

Foundries IEDM 2019 ISSCC 2020 Process Technologies

TSMC Details 5 nm

March 21, 2020May 25, 2021 David Schor 5 nm, 7 nm, EUV, N5, N5P, TSMC

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry’s highest density transistors with a high-mobility channel and highest-density SRAM cells.

Architectures Circuit Design ISSCC 2020

IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache

March 8, 2020May 25, 2021 David Schor 14HP, cache, eDRAM, IBM, IBM Z, ISSCC, ISSCC 2020, z/Architecture, z14, z15

IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of cache on the latest z15 microprocessor and system controller.

Architectures Circuit Design ISSCC 2020 Manycore Processors Server Processors

CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

March 1, 2020May 25, 2021 David Schor 28nm, 65 nm, active interposer, CEA-Leti, chiplet, interconnects, interposer, ISSCC, ISSCC 2020, multi-chip package, STMicroelectronics

CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active interposer die.

Architectures Circuit Design Graphics Processors ISSCC 2020

Radeon RX 5700: Navi and the RDNA Architecture

February 23, 2020May 25, 2021 David Schor 7 nm, AMD, ISSCC, ISSCC 2020, N7P, Navi, Radeon, Radeon RX 5700

A look at AMD’s Radeon RX 5700 GPU built on a 7-nanometer process based on the new Navi microarchitecture and RDNA graphics architecture.

Architectures Floorplanning Interconnects ISSCC 2020

7nm Boosted Zen 2 Capabilities but Doubled the Challenges

February 21, 2020May 25, 2021 David Schor 14 nm, 7 nm, AMD, capacitance, GlobalFoundries, ISSCC, ISSCC 2020, resistance, TSMC, wire delay, Zen, Zen 2

The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.