ISSCC

A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC

April 5, 2020 David Schor 1 Comment 10 nm, 22 nm, 22FFL, 3D packaging, Foveros, Intel, Lakefield, Sunny Cove, Tremont

A look at Lakefield, Intel’s new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company Foveros packaging technology.

Foundries IEDM 2019 ISSCC 2020 Process Technologies

TSMC Details 5 nm

March 21, 2020 David Schor 4 Comments 5 nm, 7 nm, EUV, N5, N5P, TSMC

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry’s highest density transistors with a high-mobility channel and highest-density SRAM cells.

Architectures Circuit Design ISSCC 2020

IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache

March 8, 2020 David Schor 5 Comments 14HP, cache, eDRAM, IBM, IBM Z, ISSCC, ISSCC 2020, z/Architecture, z14, z15

IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of cache on the latest z15 microprocessor and system controller.

Architectures Circuit Design ISSCC 2020 Manycore Processors Server Processors

CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

March 1, 2020 David Schor 0 Comments 28nm, 65 nm, active interposer, CEA-Leti, chiplet, interconnects, interposer, ISSCC, ISSCC 2020, multi-chip package, STMicroelectronics

CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active interposer die.

Architectures Circuit Design Graphics Processors ISSCC 2020

Radeon RX 5700: Navi and the RDNA Architecture

February 23, 2020 David Schor 1 Comment 7 nm, AMD, ISSCC, ISSCC 2020, N7P, Navi, Radeon, Radeon RX 5700

A look at AMD’s Radeon RX 5700 GPU built on a 7-nanometer process based on the new Navi microarchitecture and RDNA graphics architecture.

Architectures Floorplanning Interconnects ISSCC 2020

7nm Boosted Zen 2 Capabilities but Doubled the Challenges

February 21, 2020 David Schor 2 Comments 14 nm, 7 nm, AMD, capacitance, GlobalFoundries, ISSCC, ISSCC 2020, resistance, TSMC, wire delay, Zen, Zen 2

The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.

Architectures Circuit Design Floorplanning ISSCC 2018 Server Processors

ISSCC 2018: The IBM z14 Microprocessor And System Control Design

May 13, 2018 David Schor 5 Comments 14 nm, 14HP, A-Bus, floorplan, IBM, ISSCC, ISSCC 2018, mainframe, X-Bus, z/Architecture, z14

A look at the changes and enhancements that were implemented by IBM in their z14 mainframe microprocessor and system control chips.

Architectures Circuit Design ISSCC 2018 Neural Processors

QUEST, A TCI-Based 3D-Stacked SRAM Neural Processor

April 25, 2018 David Schor 0 Comments 3D packaging, 40 nm, 40LP, AI, die stacking, Hokkaido University, ISSCC, ISSCC 2018, Keio University, neural processors, process technology, TCI, ThruChip Interface, TSMC, TSV

Attempting to address the memory bandwidth problem, the QUEST neural processor uses 3D-stacked SRAM dies along with ThruChip Interface wireless communication technology to deliver sufficiently high bandwidth to sustain peak processing performance.

Architectures Circuit Design ISSCC 2018

AMD’s Zen CPU Complex, Cache, and SMU

April 18, 2018 David Schor 0 Comments 14 nm, 14LPP, AMD, cache, floorplan, ISSCC, ISSCC 2017, ISSCC 2018, SRAM, x86, Zen

A look at AMD’s Zen CPU Complex (CCX), a fully independent and modular cluster of up to four cores that are incorporated into a full SoC to form complete products such as their Zeppelin die.

Architectures Embedded Processors ISSCC 2018

ISSCC 2018: Intel’s Self-Powered Intelligent IoT Edge Mote

April 2, 2018 David Schor 0 Comments 14 nm, AI, edge computing, energy harvesting, Intel, Intel Labs, IoT, near-threshold voltage, SoC, solar power, x86

A look at Intel’s tiny intelligent IoT edge mote operating at near-threshold voltage and harvesting solar energy for charging. Equipped with sensors and an SoC with hardware to accelerate convolutional neural networks (CNNs), the chip collects environmental sensory data and captures images which are classified on-chip and sent to a data center in order to improve and optimize agricultural fields.

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