Intel Talks 10nm DTCO, EUV Benefits
Intel talks 10-nanometers DTCO and the benefits of EUV on their future 7 nm and 5 nm nodes.
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Conferences
A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip
With hybrid bonding inching towards production, here’s a look at Trishul, Arm’s first exploratory test chip – in collaboration with GlobalFoundries – that demonstrates the feasibility of high-density 3D stacking using Arm’s CoreLink CMN-600 extended to 3D.
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Samsung Details 5nm and 4nm; Adds 8LPA, 5LPP, and 4LPP Nodes; Readies 3nm GAA For Next Year
Samsung revealed more details of its 5LPE process technology which recently ramped, gave a roadmap status update along with new stop-gap nodes announcement.
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Hot Chips 33 Program: Alder Lake, Sapphire Rapids, Zen 3, Next-Gen Z, Neoverse N2, And Many More
The IEEE Symposium on High-Performance Chips Program Committee announced the program for the 2021 Hot Chips 33 conference.
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IBM Releases Power ISA v3.1; To Present POWER10 At Hot Chips 32
IBM releases Power ISA v3.1. Among the new instructions, there is new bfloat16 support, new reduced-precision outer-product operations including 4-bit integers, and new instruction prefixes. IBM plans on presenting POWER10 at Hot Chips 32.
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A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC
A look at Lakefield, Intel’s new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company Foveros packaging technology.
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TSMC Details 5 nm
TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry’s highest density transistors with a high-mobility channel and highest-density SRAM cells.
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IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache
IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of cache on the latest z15 microprocessor and system controller.
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CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor
CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active interposer die.
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Radeon RX 5700: Navi and the RDNA Architecture
A look at AMD’s Radeon RX 5700 GPU built on a 7-nanometer process based on the new Navi microarchitecture and RDNA graphics architecture.
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